Table 2-2. Core modules (continued)Module DescriptionAWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) isto detect asynchronous wake-up events in stop modes and signal to clock controllogic to resume system clocking. After clock restart, the NVIC observes thepending interrupt and performs the normal interrupt or event processing.Debug interfaces Most of this device's debug is based on the ARM CoreSight™ architecture. Fourdebug interfaces are supported:• IEEE 1149.1 JTAG• IEEE 1149.7 JTAG (cJTAG)• Serial Wire Debug (SWD)• ARM Real-Time Trace Interface2.2.2 System ModulesThe following system modules are available on this device.Table 2-3. System modulesModule DescriptionSystem integration module (SIM) The SIM includes integration logic and several module configuration settings.System mode controller The SMC provides control and protection on entry and exit to each power mode,control for the Power management controller (PMC), and reset entry and exit forthe complete MCU.Power management controller (PMC) The PMC provides the user with multiple power options that allow the user tooptimize power consumption for the level of functionality needed. Includes power-on-reset (POR) and integrated low voltage detect (LVD) with reset (brownout)capability and selectable LVD trip points.Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLSand VLLS) through various internal peripheral and external pin sources.Miscellaneous control module (MCM) The MCM includes integration logicCrossbar switch (XBS) The XBS connects bus masters and bus slaves, allowing all bus masters to accessdifferent bus slaves simultaneously and providing arbitration among the busmasters when they access the same slave.Peripheral bridges The peripheral bridge converts the crossbar switch interface to an interface toaccess a majority of peripherals on the device.DMA multiplexer (DMAMUX) The DMA multiplexer selects from many DMA requests down to a smaller numberfor the DMA controller.Direct memory access (DMA) controller The DMA controller provides programmable channels with transfer controldescriptors for data movement via dual-address transfers for 8-bit, 16-bit, 32-bit,16-byte and 32-byte data values.External watchdog monitor (EWM) The EWM is a redundant mechanism to the software watchdog module thatmonitors both internal and external system operation for fail conditions.Software watchdog (WDOG) The WDOG monitors internal system operation and forces a reset in case offailure. It can run from an independent 1 KHz low power oscillator with aprogrammable refresh window to detect deviations in program flow or systemfrequency.Chapter 2 IntroductionK22F Sub-Family Reference Manual, Rev. 4, 08/2016NXP Semiconductors 51
