high-frequency characteristics. This capacitor is connected between VREFH and VREFLand must be placed as near as possible to the package pins. Resistance in the path is notrecommended because the current causes a voltage drop that could result in conversionerrors. Inductance in this path must be minimum, that is, parasitic only.34.6.1.3 Analog input pinsThe external analog inputs are typically shared with digital I/O pins on MCU devices.Empirical data shows that capacitors on the analog inputs improve performance in thepresence of noise or when the source impedance is high. Use of 0.01 μF capacitors withgood high-frequency characteristics is sufficient. These capacitors are not necessary in allcases, but when used, they must be placed as near as possible to the package pins and bereferenced to VSSA.For proper conversion, the input voltage must fall between VREFH and VREFL. If the inputis equal to or exceeds VREFH, the converter circuit converts the signal to 0xFFF, which isfull scale 12-bit representation, 0x3FF, which is full scale 10-bit representation, or 0xFF,which is full scale 8-bit representation. If the input is equal to or less than VREFL, theconverter circuit converts it to 0x000. Input voltages between VREFH and VREFL arestraight-line linear conversions. There is a brief current associated with VREFL when thesampling capacitor is charging.For minimal loss of accuracy due to current injection, pins adjacent to the analog inputpins must not be transitioning during conversions.34.6.2 Sources of error34.6.2.1 Sampling errorFor proper conversions, the input must be sampled long enough to achieve the properaccuracy.RAS + RADIN =SC / (FMAX * NUMTAU * CADIN)Figure 34-3. Sampling equationWhere:RAS = External analog source resistanceSC = Number of ADCK cycles used during sample windowChapter 34 Analog-to-Digital Converter (ADC)K22F Sub-Family Reference Manual, Rev. 4, 08/2016NXP Semiconductors 811
