37.3.1 Voltage Reference Disabled, SC[VREFEN] = 0When SC[VREFEN] = 0, the Voltage Reference is disabled, the VREF bandgap and theoutput buffers are disabled. The Voltage Reference is in off mode.37.3.2 Voltage Reference Enabled, SC[VREFEN] = 1When SC[VREFEN] = 1, the Voltage Reference is enabled, and different modes shouldbe set by the SC[MODE_LV] bits.37.3.2.1 SC[MODE_LV]=00The internal VREF bandgap is enabled to generate an accurate 1.2 V output that can betrimmed with the TRM register's TRIM[5:0] bitfield. The bandgap requires some time forstartup and stabilization. SC[VREFST] can be monitored to determine if the stabilizationand startup is complete when the chop oscillator is not enabled.If the chop oscillator is being used, the internal bandgap reference voltage settles withinthe chop oscillator start up time, Tchop_osc_stup.The output buffer is disabled in this mode, and there is no buffered voltage output. TheVoltage Reference is in standby mode. If this mode is first selected and the low power orhigh power buffer mode is subsequently enabled, there will be a delay before the bufferoutput is settled at the final value. This is the buffer start up delay (Tstup) and the value isspecified in the appropriate device data sheet.37.3.2.2 SC[MODE_LV] = 01The internal VREF bandgap is on. The high power buffer is enabled to generate abuffered 1.2 V voltage to VREF_OUT. It can also be used as a reference to internalanalog peripherals such as an ADC channel or analog comparator input.If this mode is entered from the standby mode (SC[MODE_LV] = 00, SC[VREFEN] = 1)there will be a delay before the buffer output is settled at the final value. This is the bufferstart up delay (Tstup) and the value is specified in the appropriate device data sheet. Ifthis mode is entered when the VREF module is enabled then you must wait the longer ofChapter 37 Voltage Reference (VREFV1)K22F Sub-Family Reference Manual, Rev. 4, 08/2016NXP Semiconductors 863
