26.7.1.2 OSC_DIV (OSC_OSC_DIV)OSC Clock divider register.Address: 4006_5000h base + 2h offset = 4006_5002hBit 7 6 5 4 3 2 1 0Read ERPS 0 0 0 0 0 0WriteReset 0 0 0 0 0 0 0 0OSC_OSC_DIV field descriptionsField Description7–6ERPSERCLK prescaler. These two bits are used to divide the ERCLK output. The un-divided ERCLK output isnot affected by these two bits.00 The divisor ratio is 1.01 The divisor ratio is 2.10 The divisor ratio is 4.11 The divisor ratio is 8.5ReservedThis field is reserved.This read-only field is reserved and always has the value 0.4ReservedThis field is reserved.This read-only field is reserved and always has the value 0.3ReservedThis field is reserved.This read-only field is reserved and always has the value 0.2ReservedThis field is reserved.This read-only field is reserved and always has the value 0.1ReservedThis field is reserved.This read-only field is reserved and always has the value 0.0ReservedThis field is reserved.This read-only field is reserved and always has the value 0.26.8 Functional DescriptionFunctional details of the module can be found here.26.8.1 OSC module statesThe states of the OSC module are shown in the following figure. The states and theirtransitions between each other are described in this section.Chapter 26 Oscillator (OSC)K22F Sub-Family Reference Manual, Rev. 4, 08/2016NXP Semiconductors 583
