Table 41-1. Modes of operationModes DescriptionRun The LPTMR operates normally.WaitThe LPTMR continues to operate normally andmay be configured to exit the low-power modeby generating an interrupt request.StopThe LPTMR continues to operate normally andmay be configured to exit the low-power modeby generating an interrupt request.Low-LeakageThe LPTMR continues to operate normally andmay be configured to exit the low-power modeby generating an interrupt request.DebugThe LPTMR operates normally in Pulse Countermode, but counter does not increment in TimeCounter mode.41.2 LPTMR signal descriptionsTable 41-2. LPTMR signal descriptionsSignal I/O DescriptionLPTMR0_ALTn I Pulse Counter Input pin41.2.1 Detailed signal descriptionsTable 41-3. LPTMR interface—detailed signal descriptionsSignal I/O DescriptionLPTMR_ALTn I Pulse Counter InputThe LPTMR can select one of the input pins to be used in Pulse Counter mode.State meaning Assertion—If configured for pulse counter mode withactive-high input, then assertion causes the CNR toincrement.Deassertion—If configured for pulse counter mode withactive-low input, then deassertion causes the CNR toincrement.Timing Assertion or deassertion may occur at any time; input mayassert asynchronously to the bus clock.41.3 Memory map and register definitionLPTMR signal descriptionsK22F Sub-Family Reference Manual, Rev. 4, 08/20161042 NXP Semiconductors
