Section number Title Page37.3 Functional Description..................................................................................................................................................86237.3.1 Voltage Reference Disabled, SC[VREFEN] = 0......................................................................................... 86337.3.2 Voltage Reference Enabled, SC[VREFEN] = 1.......................................................................................... 86337.3.3 Internal voltage regulator............................................................................................................................. 86437.4 Initialization/Application Information.......................................................................................................................... 865Chapter 38Programmable Delay Block (PDB)38.1 Introduction...................................................................................................................................................................86738.1.1 Features........................................................................................................................................................ 86738.1.2 Implementation............................................................................................................................................ 86838.1.3 Back-to-back acknowledgment connections................................................................................................86938.1.4 DAC External Trigger Input Connections................................................................................................... 86938.1.5 Block diagram.............................................................................................................................................. 86938.1.6 Modes of operation...................................................................................................................................... 87138.2 PDB signal descriptions................................................................................................................................................87138.3 Memory map and register definition.............................................................................................................................87138.3.1 Status and Control register (PDBx_SC).......................................................................................................87338.3.2 Modulus register (PDBx_MOD).................................................................................................................. 87638.3.3 Counter register (PDBx_CNT).....................................................................................................................87638.3.4 Interrupt Delay register (PDBx_IDLY)....................................................................................................... 87738.3.5 Channel n Control register 1 (PDBx_CHnC1).............................................................................................87738.3.6 Channel n Status register (PDBx_CHnS).....................................................................................................87838.3.7 Channel n Delay 0 register (PDBx_CHnDLY0)..........................................................................................87938.3.8 Channel n Delay 1 register (PDBx_CHnDLY1)..........................................................................................88038.3.9 DAC Interval Trigger n Control register (PDBx_DACINTCn)...................................................................88038.3.10 DAC Interval n register (PDBx_DACINTn)............................................................................................... 88138.3.11 Pulse-Out n Enable register (PDBx_POEN)................................................................................................ 88238.3.12 Pulse-Out n Delay register (PDBx_POnDLY).............................................................................................88238.4 Functional description...................................................................................................................................................883K22F Sub-Family Reference Manual, Rev. 4, 08/201630 NXP Semiconductors
