Chapter 4Memory Map4.1 IntroductionThis device contains various memories and memory-mapped peripherals which arelocated in one 32-bit contiguous memory space. This chapter describes the memory andperipheral locations within that memory space.4.2 System memory mapThe following table shows the high-level device memory map. This map provides thecomplete architectural address space definition for the various sections. Based on thephysical sizes of the memories and peripherals, the actual address regions used may besmaller.The system memory map includes address spaces that are intended for specific purposes.• The two ICode regions (address < 0x2000_0000) mapped to the FlexBus space allowcode to be executed with maximum performance.• There is an aliased region that maps a system address space to the Program flashsection. Flash region aliasing is specifically intended for references to read-only datacoefficients in the flash while still preserving a full Harvard memory organization inthe processor core supporting concurrent instruction fetches (for example, fromRAM) and data accesses (from flash via the aliased space).• The bitbanding functionality supported by the processor core uses aliased regionsthat map to the basic RAM and peripheral address spaces. This functionality mapseach 32-bit word of the aliased address space to a unique bit in the underlying RAMor peripheral address space to support single-bit insert and extract operations fromthe processor.K22F Sub-Family Reference Manual, Rev. 4, 08/2016NXP Semiconductors 139
