28.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL)The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways arenumbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, xdenotes the way, y denotes the set, and U and L represent upper and lower word,respectively. This section represents data for the lower word (bits [31:0]) of all sets in theindicated way.Address: 4001_F000h base + 244h offset + (8d × i), where i=0d to 7dBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R data[31:0]WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FMC_DATAW1SnL field descriptionsField Descriptiondata[31:0] Bits [31:0] of data entry28.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU)The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways arenumbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, xdenotes the way, y denotes the set, and U and L represent upper and lower word,respectively. This section represents data for the upper word (bits [63:32]) of all sets inthe indicated way.Address: 4001_F000h base + 280h offset + (8d × i), where i=0d to 7dBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R data[63:32]WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FMC_DATAW2SnU field descriptionsField Descriptiondata[63:32] Bits [63:32] of data entryMemory map and register descriptionsK22F Sub-Family Reference Manual, Rev. 4, 08/2016612 NXP Semiconductors
