NXP Semiconductors K22F series manuals

K22F series

Brand: NXP Semiconductors | Category: Controller

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Table Of Contents
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Overview
Typographic notation
ARM® Cortex®-M4 Core Modules
System Modules
Memories and Memory Interfaces
Security and Integrity modules
Communication interfaces
Human-machine interfaces
Introduction
Nested Vectored Interrupt Controller (NVIC) Configuration
Asynchronous Wake-up Interrupt Controller (AWIC) Configuration
FPU Configuration
JTAG Controller Configuration
System Mode Controller (SMC) Configuration
PMC Configuration
MCM Configuration
Peripheral Bridge Configuration
DMA request multiplexer configuration
DMA Controller Configuration
External Watchdog Monitor (EWM) Configuration
Watchdog Configuration
Clock modules
OSC Configuration
Flash Memory Controller Configuration
System Register File Configuration
VBAT Register File Configuration
EzPort Configuration
FlexBus Configuration
Security
RNG Configuration
Analog
CMP Configuration
bit DAC Configuration
VREF Configuration
Timers
FlexTimer Configuration
PIT Configuration
Low-power timer configuration
RTC configuration
SPI configuration
I2C Configuration
UART Configuration
LPUART configuration
Memory Map
Aliased bit-band regions
Flash Access Control Introduction
Alternate Non-Volatile IRC User Trim Description
Peripheral bridge (AIPS-Lite) memory map
Peripheral Bridge 0 (AIPS-Lite 0) Memory Map
Private Peripheral Bus (PPB) memory map
Clock definitions
Device clock summary
Internal clocking requirements
Clock divider values after reset
Clock Gating
PMC 1-kHz LPO clock
WDOG clocking
PORT digital filter clocking
RTC_CLKOUT and CLKOUT32K clocking
USB FS OTG Controller clocking
UART clocking
Reset
MCU Resets
Reset Pin
Debug resets
Boot
FOPT boot options
Boot sequence
DMA Wakeup
Compute Operation
Peripheral Doze
Entering and exiting power modes
Power mode transitions
Power modes shutdown sequencing
Flash Program Restrictions
Security Interactions with other Modules
Debug
References
JTAG-to-SWD change sequence
Debug Port Pin Descriptions
JTAG status and control registers
MDM-AP Control Register
MDM-AP Status Register
AHB-AP
Core Trace Connectivity
Debug in Low Power Modes
Debug Module State in Low Power Modes
Port control and interrupt module features
K22 Pinouts
Module Signal Description Tables
Core Modules
Timer Modules
Human-Machine Interfaces (HMI)
Modes of operation
External signal description
Pin Control Register n (PORTx_PCRn)
Global Pin Control Low Register (PORTx_GPCLR)
Interrupt Status Flag Register (PORTx_ISFR)
Digital Filter Clock Register (PORTx_DFCR)
Functional description
Global pin control
Digital filter
Memory map and register definition
System Options Register 1 (SIM_SOPT1)
SOPT1 Configuration Register (SIM_SOPT1CFG)
System Options Register 2 (SIM_SOPT2)
System Options Register 4 (SIM_SOPT4)
System Options Register 5 (SIM_SOPT5)
System Options Register 7 (SIM_SOPT7)
System Options Register 8 (SIM_SOPT8)
System Device Identification Register (SIM_SDID)
System Clock Gating Control Register 4 (SIM_SCGC4)
System Clock Gating Control Register 5 (SIM_SCGC5)
System Clock Gating Control Register 6 (SIM_SCGC6)
System Clock Gating Control Register 7 (SIM_SCGC7)
System Clock Divider Register 1 (SIM_CLKDIV1)
System Clock Divider Register 2 (SIM_CLKDIV2)
Flash Configuration Register 1 (SIM_FCFG1)
Flash Configuration Register 2 (SIM_FCFG2)
Unique Identification Register High (SIM_UIDH)
Unique Identification Register Mid Low (SIM_UIDML)
Chip-Specific Information
Clock Configuration
Flashloader Protocol
Flashloader Packet Types
Flashloader Command API
Peripherals Supported
I2C Peripheral
SPI Peripheral
UART Peripheral
USB peripheral
Get/SetProperty Command Properties
Property Definitions
Kinetis Flashloader Status Error Codes
Introduction
System Reset Status Register 0 (RCM_SRS0)
System Reset Status Register 1 (RCM_SRS1)
Reset Pin Filter Control register (RCM_RPFC)
Reset Pin Filter Width register (RCM_RPFW)
Mode Register (RCM_MR)
Sticky System Reset Status Register 0 (RCM_SSRS0)
Sticky System Reset Status Register 1 (RCM_SSRS1)
Memory map and register descriptions
Power Mode Protection register (SMC_PMPROT)
Power Mode Control register (SMC_PMCTRL)
Stop Control Register (SMC_STOPCTRL)
Power Mode Status register (SMC_PMSTAT)
Power mode entry/exit sequencing
Run modes
Wait modes
LVD reset operation
I/O retention
Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)
Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)
Regulator Status And Control register (PMC_REGSC)
Block diagram
LLWU signal descriptions
LLWU Pin Enable 1 register (LLWU_PE1)
LLWU Pin Enable 2 register (LLWU_PE2)
LLWU Pin Enable 3 register (LLWU_PE3)
LLWU Pin Enable 4 register (LLWU_PE4)
LLWU Module Enable register (LLWU_ME)
LLWU Flag 1 register (LLWU_F1)
LLWU Flag 2 register (LLWU_F2)
LLWU Flag 3 register (LLWU_F3)
LLWU Pin Filter 1 register (LLWU_FILT1)
LLWU Pin Filter 2 register (LLWU_FILT2)
LLS mode
Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
Crossbar Switch (AXBS) Control Register (MCM_PLACR)
Compute Operation Control Register (MCM_CPO)
Memory Map / Register Definition
Arbitration
Initialization/application information
Memory map/register definition
Features
Channel Configuration register (DMAMUX_CHCFGn)
DMA channels with no triggering capability
Always-enabled DMA sources
Block parts
TCD structure
Control Register (DMA_CR)
Error Status Register (DMA_ES)
Enable Request Register (DMA_ERQ)
Enable Error Interrupt Register (DMA_EEI)
Clear Enable Error Interrupt Register (DMA_CEEI)
Set Enable Error Interrupt Register (DMA_SEEI)
Clear Enable Request Register (DMA_CERQ)
Set Enable Request Register (DMA_SERQ)
Clear DONE Status Bit Register (DMA_CDNE)
Set START Bit Register (DMA_SSRT)
Clear Error Register (DMA_CERR)
Clear Interrupt Request Register (DMA_CINT)
Interrupt Request Register (DMA_INT)
Error Register (DMA_ERR)
Hardware Request Status Register (DMA_HRS)
Enable Asynchronous Request in Stop Register (DMA_EARS)
Channel n Priority Register (DMA_DCHPRIn)
TCD Source Address (DMA_TCDn_SADDR)
TCD Transfer Attributes (DMA_TCDn_ATTR)
TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled DMA_TCDn_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled DMA_TCDn_NBYTES_MLOFFYES)
TCD Last Source Address Adjustment (DMA_TCDn_SLAST)
TCD Destination Address (DMA_TCDn_DADDR)
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled DMA_TCDn_CITER_ELINKYES)
TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)
TCD Control and Status (DMA_TCDn_CSR)
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled DMA_TCDn_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled DMA_TCDn_BITER_ELINKNO)
Fault reporting and handling
Channel preemption
Programming errors
Arbitration mode considerations
Monitoring transfer descriptor status
Channel Linking
Dynamic programming
Lockstep
EWM Signal Descriptions
Service Register (EWM_SERV)
Compare High Register (EWM_CMPH)
Clock Prescaler Register (EWM_CLKPRESCALER)
The EWM_in Signal
EWM Counter
EWM Interrupt
Functional overview
Unlocking and updating the watchdog
Watchdog configuration time (WCT)
Refreshing the watchdog
Debug modes of operation
Quick test
Backup reset generator
Generated resets and interrupts
Watchdog Status and Control Register High (WDOG_STCTRLH)
Watchdog Status and Control Register Low (WDOG_STCTRLL)
Watchdog Time-out Value Register Low (WDOG_TOVALL)
Watchdog Window Register Low (WDOG_WINL)
Watchdog Timer Output Register High (WDOG_TMROUTH)
Watchdog Reset Count register (WDOG_RSTCNT)
Refresh and unlock operations with 8-bit access
Restrictions on watchdog operation
MCG Control 1 Register (MCG_C1)
MCG Control 2 Register (MCG_C2)
MCG Control 3 Register (MCG_C3)
MCG Control 4 Register (MCG_C4)
MCG Control 5 Register (MCG_C5)
MCG Control 6 Register (MCG_C6)
MCG Status Register (MCG_S)
MCG Status and Control Register (MCG_SC)
MCG Auto Trim Compare Value High Register (MCG_ATCVH)
MCG Control 8 Register (MCG_C8)
MCG Control 12 Register (MCG_C12)
MCG Test 3 Register (MCG_T3)
Low-power bit usage
External Reference Clock
MCG Fixed Frequency Clock
Initialization / Application information
Using a 32.768 kHz reference
External Crystal / Resonator Connections
External Clock Connections
Memory Map/Register Definitions
OSC module modes
Counter
Low power modes operation
RTC Signal Descriptions
External Crystal Connections
Reset Overview
Flash Access Protection Register (FMC_PFAPR)
Flash Bank 0 Control Register (FMC_PFB0CR)
Flash Bank 1 Control Register (FMC_PFB1CR)
Cache Tag Storage (FMC_TAGVDW0Sn)
Cache Tag Storage (FMC_TAGVDW1Sn)
Cache Tag Storage (FMC_TAGVDW2Sn)
Cache Tag Storage (FMC_TAGVDW3Sn)
Cache Data Storage (lower word) (FMC_DATAW0SnL)
Cache Data Storage (lower word) (FMC_DATAW1SnL)
Cache Data Storage (lower word) (FMC_DATAW2SnL)
Cache Data Storage (lower word) (FMC_DATAW3SnL)
Configuration options
Flash Access Control (FAC) Function
Initialization and application information
Glossary
Memory Map and Registers
Register Descriptions
Flash Access Protection
Interrupts
Flash Operation in Low-Power Modes
Read While Write (RWW)
Margin Read Commands
Flash Command Description
Reset Sequence
External signal descriptions
EzPort Chip Select (EZP_CS)
Command descriptions
Flash memory map for EzPort access
Chip Select Address Register (FB_CSARn)
Chip Select Mask Register (FB_CSMRn)
Chip Select Control Register (FB_CSCRn)
Chip Select port Multiplexing Control Register (FB_CSPMCR)
Address comparison
Bit ordering
Address/data bus multiplexing
Data transfer states
FlexBus Timing Examples
Burst cycles
Extended Transfer Start/Address Latch Enable
Bus errors
CRC Data register (CRC_DATA)
CRC Polynomial register (CRC_GPOLY)
CRC initialization/reinitialization
Transpose feature
CRC result complement
Entering Sleep mode
RNGA Status Register (RNG_SR)
RNGA Entropy Register (RNG_ER)
ADC signal descriptions
Voltage Reference Select
Analog Channel Inputs (ADx)
ADC Status and Control Registers 1 (ADCx_SC1n)
ADC Configuration Register 1 (ADCx_CFG1)
ADC Configuration Register 2 (ADCx_CFG2)
ADC Data Result Register (ADCx_Rn)
Compare Value Registers (ADCx_CVn)
Status and Control Register 2 (ADCx_SC2)
Status and Control Register 3 (ADCx_SC3)
ADC Offset Correction Register (ADCx_OFS)
ADC Plus-Side Gain Register (ADCx_PG)
ADC Plus-Side General Calibration Value Register (ADCx_CLPD)
ADC Plus-Side General Calibration Value Register (ADCx_CLPS)
ADC Plus-Side General Calibration Value Register (ADCx_CLP3)
ADC Plus-Side General Calibration Value Register (ADCx_CLP1)
ADC Minus-Side General Calibration Value Register (ADCx_CLMD)
ADC Minus-Side General Calibration Value Register (ADCx_CLM4)
ADC Minus-Side General Calibration Value Register (ADCx_CLM2)
ADC Minus-Side General Calibration Value Register (ADCx_CLM0)
Clock select and divide control
Voltage reference selection
Conversion control
Automatic compare function
Calibration function
User-defined offset function
Temperature sensor
MCU wait mode operation
MCU Low-Power Stop mode operation
Initialization information
Application information
Sources of error
bit DAC key features
ANMUX key features
CMP block diagram
CMP Control Register 1 (CMPx_CR1)
CMP Filter Period Register (CMPx_FPR)
DAC Control Register (CMPx_DACCR)
MUX Control Register (CMPx_MUXCR)
Power modes
Startup and operation
Low-pass filter
CMP interrupts
CMP Asynchronous DMA support
Digital-to-analog converter
DAC resets
DAC Data Low Register (DACx_DATnL)
DAC Status Register (DACx_SR)
DAC Control Register (DACx_C0)
DAC Control Register 1 (DACx_C1)
DAC Control Register 2 (DACx_C2)
DMA operation
VREF Status and Control Register (VREF_SC)
Voltage Reference Disabled, SC[VREFEN] = 0
Internal voltage regulator
Implementation
Back-to-back acknowledgment connections
Status and Control register (PDBx_SC)
Modulus register (PDBx_MOD)
Interrupt Delay register (PDBx_IDLY)
Channel n Status register (PDBx_CHnS)
Channel n Delay 0 register (PDBx_CHnDLY0)
Channel n Delay 1 register (PDBx_CHnDLY1)
DAC Interval n register (PDBx_DACINTn)
Pulse-Out n Enable register (PDBx_POEN)
PDB trigger input source selection
Updating the delay registers
Impact of using the prescaler and multiplication factor on timing resolution
FTM signal descriptions
Status And Control (FTMx_SC)
Counter (FTMx_CNT)
Modulo (FTMx_MOD)
Channel (n) Status And Control (FTMx_CnSC)
Channel (n) Value (FTMx_CnV)
Capture And Compare Status (FTMx_STATUS)
Features Mode Selection (FTMx_MODE)
Synchronization (FTMx_SYNC)
Initial State For Channels Output (FTMx_OUTINIT)
Output Mask (FTMx_OUTMASK)
Function For Linked Channels (FTMx_COMBINE)
Deadtime Insertion Control (FTMx_DEADTIME)
FTM External Trigger (FTMx_EXTTRIG)
Channels Polarity (FTMx_POL)
Fault Mode Status (FTMx_FMS)
Input Capture Filter Control (FTMx_FILTER)
Fault Control (FTMx_FLTCTRL)
Quadrature Decoder Control And Status (FTMx_QDCTRL)
Configuration (FTMx_CONF)
FTM Fault Input Polarity (FTMx_FLTPOL)
Synchronization Configuration (FTMx_SYNCONF)
FTM Inverting Control (FTMx_INVCTRL)
FTM Software Output Control (FTMx_SWOCTRL)
FTM PWM Load (FTMx_PWMLOAD)
Clock source
Prescaler
Input Capture mode
Output Compare mode
Edge-Aligned PWM (EPWM) mode
Center-Aligned PWM (CPWM) mode
Combine mode
Complementary mode
Registers updated from write buffers
PWM synchronization
Inverting
Software output control
Deadtime insertion
Output mask
Fault control
Polarity control
Initialization
Channel trigger output
Initialization trigger
Capture Test mode
Dual Edge Capture mode
Quadrature Decoder mode
BDM mode
Intermediate load
Global time base (GTB)
FTM Interrupts
Timer Overflow Interrupt
Memory map/register description
Timer Load Value Register (PIT_LDVALn)
Timer Control Register (PIT_TCTRLn)
Example configuration for chained timers
LPTMR signal descriptions
Low Power Timer Control Status Register (LPTMRx_CSR)
Low Power Timer Prescale Register (LPTMRx_PSR)
Low Power Timer Compare Register (LPTMRx_CMR)
LPTMR compare
LPTMR hardware trigger
Register definition
RTC Time Prescaler Register (RTC_TPR)
RTC Time Compensation Register (RTC_TCR)
RTC Control Register (RTC_CR)
RTC Status Register (RTC_SR)
RTC Lock Register (RTC_LR)
RTC Interrupt Enable Register (RTC_IER)
RTC Write Access Register (RTC_WAR)
RTC Read Access Register (RTC_RAR)
Time counter
Compensation
Update mode
USB On-The-Go
USBFS Features
On-chip transceiver required external components
Programmers interface
RX vs. TX as a USB peripheral device or USB host
Addressing BDT entries
Buffer Descriptors (BDs)
USB transaction
Peripheral ID register (USBx_PERID)
Peripheral ID Complement register (USBx_IDCOMP)
Peripheral Additional Info register (USBx_ADDINFO)
OTG Interrupt Control register (USBx_OTGICR)
OTG Status register (USBx_OTGSTAT)
OTG Control register (USBx_OTGCTL)
Interrupt Status register (USBx_ISTAT)
Interrupt Enable register (USBx_INTEN)
Error Interrupt Status register (USBx_ERRSTAT)
Error Interrupt Enable register (USBx_ERREN)
Status register (USBx_STAT)
Control register (USBx_CTL)
Address register (USBx_ADDR)
BDT Page register 1 (USBx_BDTPAGE1)
Frame Number register High (USBx_FRMNUMH)
SOF Threshold register (USBx_SOFTHLD)
BDT Page Register 2 (USBx_BDTPAGE2)
Endpoint Control register (USBx_ENDPTn)
USB Control register (USBx_USBCTRL)
USB OTG Observe register (USBx_OBSERVE)
USB Transceiver Control register 0 (USBx_USBTRC0)
Frame Adjust Register (USBx_USBFRMADJUST)
USB Clock recovery control (USBx_CLK_RECOVER_CTRL)
IRC48M oscillator enable register (USBx_CLK_RECOVER_IRC_EN)
Clock recovery combined interrupt enable (USBx_CLK_RECOVER_INT_EN)
OTG and Host mode operation
On-The-Go operation
OTG dual role A device operation
OTG dual role B device operation
Device mode IRC48 operation
Interface configurations
Module signal descriptions
PCS1–PCS3—Peripheral Chip Selects 1–3
SIN—Serial Input
Module Configuration Register (SPIx_MCR)
Transfer Count Register (SPIx_TCR)
Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn)
Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTARn_SLAVE)
Status Register (SPIx_SR)
DMA/Interrupt Request Select and Enable Register (SPIx_RSER)
PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)
PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE)
Transmit FIFO Registers (SPIx_TXFRn)
Start and Stop of module transfers
Serial Peripheral Interface (SPI) configuration
Module baud rate and clock delay generation
Transfer formats
Continuous Serial Communications Clock
Slave Mode Operation Constraints
Power saving features
How to manage queues
Initializing Module in Master/Slave Modes
Delay settings
Calculation of FIFO pointer addresses
I2C Address Register 1 (I2Cx_A1)
I2C Control Register 1 (I2Cx_C1)
I2C Status register (I2Cx_S)
I2C Data I/O register (I2Cx_D)
I2C Programmable Input Glitch Filter Register (I2Cx_FLT)
I2C Range Address register (I2Cx_RA)
I2C Address Register 2 (I2Cx_A2)
I2C SCL Low Timeout Register Low (I2Cx_SLTL)
bit address
Address matching
System management bus specification
Resets
Programmable input glitch filter
DMA support
UART signal descriptions
UART Baud Rate Registers: High (UARTx_BDH)
UART Baud Rate Registers: Low (UARTx_BDL)
UART Control Register 1 (UARTx_C1)
UART Control Register 2 (UARTx_C2)
UART Status Register 1 (UARTx_S1)
UART Status Register 2 (UARTx_S2)
UART Control Register 3 (UARTx_C3)
UART Data Register (UARTx_D)
UART Match Address Registers 1 (UARTx_MA1)
UART Match Address Registers 2 (UARTx_MA2)
UART Control Register 5 (UARTx_C5)
UART Extended Data Register (UARTx_ED)
UART Modem Register (UARTx_MODEM)
UART Infrared Register (UARTx_IR)
UART FIFO Parameters (UARTx_PFIFO)
UART FIFO Control Register (UARTx_CFIFO)
UART FIFO Status Register (UARTx_SFIFO)
UART FIFO Transmit Watermark (UARTx_TWFIFO)
UART FIFO Transmit Count (UARTx_TCFIFO)
UART FIFO Receive Count (UARTx_RCFIFO)
UART 7816 Interrupt Enable Register (UARTx_IE7816)
UART 7816 Interrupt Status Register (UARTx_IS7816)
UART 7816 Wait Parameter Register (UARTx_WP7816)
UART 7816 Wait FD Register (UARTx_WF7816)
UART 7816 Transmit Length Register (UARTx_TL7816)
UART 7816 ATR Duration Timer Register B (UARTx_AP7816B_T0)
UART 7816 Wait Parameter Register A (UARTx_WP7816A_T0)
UART 7816 Wait Parameter Register B (UARTx_WP7816B_T0)
UART 7816 Wait and Guard Parameter Register (UARTx_WGP7816_T1)
Receiver
Baud rate generation
Data format (non ISO-7816)
Single-wire operation
Loop operation
Infrared interface
Initialization sequence (non ISO-7816)
Overrun (OR) flag implications
Overrun NACK considerations
Match address registers
IrDA minimum pulse width
Legacy and reverse compatibility considerations
LPUART Baud Rate Register (LPUARTx_BAUD)
LPUART Status Register (LPUARTx_STAT)
LPUART Control Register (LPUARTx_CTRL)
LPUART Data Register (LPUARTx_DATA)
LPUART Match Address Register (LPUARTx_MATCH)
Transmitter functional description
Receiver functional description
Additional LPUART functions
Interrupts and status flags
External signals
SAI Transmit Control Register (I2Sx_TCSR)
SAI Transmit Configuration 1 Register (I2Sx_TCR1)
SAI Transmit Configuration 2 Register (I2Sx_TCR2)
SAI Transmit Configuration 3 Register (I2Sx_TCR3)
SAI Transmit Configuration 4 Register (I2Sx_TCR4)
SAI Transmit Configuration 5 Register (I2Sx_TCR5)
SAI Transmit Data Register (I2Sx_TDRn)
SAI Transmit Mask Register (I2Sx_TMR)
SAI Receive Control Register (I2Sx_RCSR)
SAI Receive Configuration 1 Register (I2Sx_RCR1)
SAI Receive Configuration 3 Register (I2Sx_RCR3)
SAI Receive Configuration 4 Register (I2Sx_RCR4)
SAI Receive Configuration 5 Register (I2Sx_RCR5)
SAI Receive FIFO Register (I2Sx_RFRn)
SAI MCLK Control Register (I2Sx_MCR)
SAI MCLK Divide Register (I2Sx_MDR)
SAI resets
Synchronous modes
Frame sync configuration
Word mask register
GPIO signal descriptions
Memory map and register definition
Port Data Output Register (GPIOx_PDOR)
Port Set Output Register (GPIOx_PSOR)
Port Clear Output Register (GPIOx_PCOR)
Port Data Input Register (GPIOx_PDIR)
Register description
Device identification register
JTAGC block instructions
Boundary scan

NXP Semiconductors K22F series manuals

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K22F series