Virtex-4 RocketIO MGT User Guide www.xilinx.com 101UG076 (v4.1) November 2, 2008RChapter 3PCS Digital Design ConsiderationsThe Virtex®-4 RocketIO™ MGT PCS supports 8B/10B encode/decode, SONETcompatibility, and generic data modes. The MGT operates in two basic internal modes:32 bit and 40 bit. Applications can change PMA rates and PCS protocol settings atconfiguration time or at run-time. Internal data width, external data width, and datarouting can all be configured on a clock-by-clock basis.Note: The configuration task described in this chapter can be performed using the RocketIO wizard.The wizard also provides example designs and simulations to demonstrate the use model for eachfeature.Top-Level ArchitectureTransmit ArchitectureThe transmit architecture for the PCS is shown in Figure 3-1. For information aboutbypassing particular blocks, consult the block function section for that block.Note: The TX and RX CRC blocks can be run independently of the MGT. See Chapter 5, “CyclicRedundancy Check (CRC)” for more information.Receive ArchitectureThe receive architecture for the PCS is shown in Figure 3-2. For information aboutbypassing particular blocks, consult the block function section for that particular block.Figure 3-1: Transmit Architecture8x40 bitTX RingBuffer 8B/10BEncode64B/66BGearbox(1)10GBASE-REncode (1)TXUSRCLKTXUSRCLK2TXENC8B10BUSETXENC64B66BUSEPMA64B/66BScrambler(1)PISOTX_BUFFER_USE ResetControlPMAAttributesFabric InterfaceUG035_CH3_01_071807TXDATATXRESETTXPTXNTXSCRAM64B66BUSETXGEARBOX64B66BUSE TXPOLARITYTXDATA_SELNote: (1) 64B/66B encoding/decoding is not supported.
