Virtex-4 RocketIO MGT User Guide www.xilinx.com 155UG076 (v4.1) November 2, 2008FunctionalityRFunctionalityThe 32-bit CRC block is a CRC generator using the following polynomial:G(x) = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1.An important feature of the block is its ability to work at twice the speed ofRX/TXCRCINTCLK when the fabric data width is twice the internal data width, as shownin Figure 5-2. When the attribute RXCRCCLKDOUBLE / TXCRCCLKDOUBLE is set toTRUE, the ratio between RXCRCINTCLK / TXCRCINTCLK and RXCRCCLK /TXCRCCLK frequencies is 1:2. The maximum interface data width is 64 bits. This allows amaximum supported data rate of 16 Gb/s at 64-bit RXCRCIN / TXCRCIN data width,with RXCRCINTCLK / TXCRCINTCLK and RXCRCCLK / TXCRCCLK at 250 MHz and500 MHz respectively. See Table 5-3 for all possible combinations of clock frequency anddata widths. Data widths supported, shown in Table 5-4, are 8, 16, 24, 32, 40, 48, 56, and 64bits. The data width can be changed by CRCDATAWIDTH at any time to support changein data rate and end-of-packet residue. (Packet length is assumed to be a multiple of bytes.)TXCRCINITVALSets the transmitter CRC initial value. This must be defined for eachprotocol that uses 32-bit CRC:Protocol Default Init ValueEthernet32’h 0000 000032’h FFFF FFFFPCI-ExpressInfinibandFibre ChannelSerial ATA 32’h 5232 5032RapidIO (1) N/ATXCRCCLKDOUBLE Allows ratio of 2:1 for TXCRCCLK and TXCRCINTCLK.TXCRCSAMECLOCKTRUE/FALSE. Select single clock mode for TX CRC.TRUE: the fabric interface clock rate is the same as the internalclock rate (TXCRCCLOCKDOUBLE is FALSE); the CRC fabricinterface and internal logic are being clocked usingTXCRCINTCLK. This attribute is typically set to TRUE whenTXCRCCLOCKDOUBLE is set to FALSE.FALSE: the clocks are being supplied to both the TXCRCCLKand TXCRCINTCLK ports.See Chapter 5, “Cyclic Redundancy Check (CRC),” for details.TXCRCENABLE Enables the TX CRC block. Default = FALSE. User must assertTRUE in the design to enable CRC.TXCRCINVERTGENFALSE/TRUE. Inverts the transmitter CRC clock.FALSE = CRC clock not inverted (default)TRUE = CRC clock inverted. During normal operation thisshould always be set to FALSE.Notes:1. RapidIO uses a 16-bit CRC, which cannot be generated or checked using the MGT’s CRC-32 block.Table 5-2: CRC Attributes (Continued)Attribute Function
