84 www.xilinx.com Virtex-4 RocketIO MGT User GuideUG076 (v4.1) November 2, 2008Chapter 2: Clocking, Timing, and Resets R• Set RXPMARESET to logic 1 at startup for a minimum of three USRCLK cycles (basedon internal data width).• Do not use the output clocks of the MGT for clocking this reset.TXRESETThe TXRESET is used to bring every flip-flop in the TX PCS to a known value but does notaffect the PMA. When TXRESET is set to logic 1, the TX PCS is considered to be in reset.Below is a list of requirements for TXRESET:• Need to have stable clock on both the TXUSRCLK and PCS TXCLK domains on thedeassertion of TXRESET to obtain reliable pointer initialization of the TX buffer. (SeeFigure 2-8, “PCS Transmit Clocking Domains and Datapaths,” page 75.)• Set TXRESET signal to logic 1 for a minimum of three cycles of the slowest frequencyon TXUSRCLK or TXUSRCLK2.• After deassertion of TXRESET, the TX PCS takes five cycles of the slowest frequencyon TXUSRCLK or TXUSRCLK2 for each clock domain to come out of reset.• For 8-byte external data interface widths, TXRESET should be deassertedsynchronously to the falling edge of TXUSRCLK2 clock to ensure proper transmitdata ordering. See Figure 2-24, “TXRESET for 8-Byte External Data Interface Width,”page 100.The blocks affected by TXRESET are:• Tx Fabric Interface — TXUSRCLK and TXUSRCLK2 domains• 8B/10B Encode — TXUSRCLK domain• Tx Buffer — TXUSRCLK and PCS TXCLK domainsSee Figure 2-8, “PCS Transmit Clocking Domains and Datapaths,” page 75.While TXRESET is asserted, the transmit data going into the PMA is all 0s.RXRESETThe RXRESET is used to bring every flip-flop in the RX PCS to a known value but does notaffect the PMA. When the signal RXRESET is set to a logic 1, the RX PCS is considered inreset. Below is a list of requirements for RXRESET:• Need to have stable clock on both the RXUSRCLK and PCS RXCLK domains on thedeassertion of RXRESET to obtain reliable pointer initialization of the RX buffer. (SeeFigure 2-7, “PCS Receive Clocking Domains and Datapaths,” page 74.)• Set RXRESET signal to logic 1 for a minimum of three cycles of the slowest frequencyon RXUSRCLK or RXUSRCLK2.• After deassertion of RXRESET, the RX PCS takes five cycles of the slowest frequencyon RXUSRCLK or RXUSRCLK2 for each clock domain to come out of reset.• When channel bonding is used in conjunction with 1-byte and 2-byte external datainterface widths, RXRESET must be deasserted synchronously on all channel-bondedMGTs with respect to RXUSRCLK2.The blocks affected by RXRESET are:• RX Fabric Interface — RXUSRCLK and RXUSRCLK2 domains• 8B/10B Decode — RXUSRCLK domain
