78 www.xilinx.com Virtex-4 RocketIO MGT User GuideUG076 (v4.1) November 2, 2008Chapter 2: Clocking, Timing, and Resets RFigure 2-11: Receive Clocking Decision Flow (Page 1 of 2)is linerate >5Gis line rate>2.5GNONONONORXOUTDIV2SEL= /1VCO rate = linerate/2= /2VCO rate = linerate= /4VCO rate = 2*linerate= /1VCO rate = 4*linerate= /2VCO rate =8*line rateSet RXPLLNDIVSEL (1)= VCO rate/refclkNOYESYESYESYESYESSTARTline rateSAMPLE_8X= TRUESAMPLE_8X= TRUEENABLE_DCDR= FALSERXDIGRX = FALSETurn offRXMCLK(2)?RXCLKMODE[0]= 0RXCLKMODE[3]= 0RXCLKMODE[0]=1RXCLKMODE[3]= 0YESNO2 byte fabricinterfaceDIGRX_FWDCLK= 00DIGRX_FWDCLK= 01DIGRX_FWDCLK= 101 byte fabricinterfaceYESYESNONO1. Modify refclk frequency for valid (8, 10, 16, 20, 32, 40)RXPLLNDIVSEL values. The lower value generates betterperformance.2. RXMCLK clock port is not supported.3. Channel Bonding, Clock Correction, and 8-byte fabricinterface are not available in low latency mode.4. RXRECCLK1 and RXRECCLK2 are never the same in themode when RXRECCLK2_USE_SYNC is set to falseregardless of low latency mode usage. There is no use modelthat needs these to be the same.5. Max serial rate for 1 byte I/F is 2.5 Gb/s.Max serial rate for 2 byte I/F is 5.0 Gb/s.6. This mode requires that USRCLK be provided by the fabric.7. Channel Bonding requires that the USRCLK is provided via thefabric.8. 64B/66B encoding/decoding is not supported.ug076_ch2_08a_071807RXOUTDIV2SEL RXOUTDIV2SEL RXOUTDIV2SEL RXOUTDIV2SELIs fabricinterface4 bytes?Is line rate>1.25GIs line rate>0.625G(cont'd on next page)ENABLE_DCDR= FALSERXDIGRX=FALSEENABLE_DCDR= FALSERXDIGRX=FALSEENABLE_DCDR= TRUERXDIGRX= TRUE<0.625G
