Virtex-4 RocketIO MGT User Guide www.xilinx.com 67UG076 (v4.1) November 2, 2008Clock DistributionRFabric ClocksThere are two cases, illustrated here in Figure 2-3:a. Direct connection to single tile (two MGTs) from GREFCLK pin, which does notuse the GT11CLK_MGT module.b. REFCLK1 or REFCLK2 column bus routing by connecting the fabric clock to theREFCLK input of the GT11CLK module.Figure 2-3: REFCLK and GREFCLK Options for an MGT TileGT11_inst1REFCLK1GT11CLK_inst1SYNCLK1OUTEN = ENABLESYNCLK2OUTEN = DISABLEREFCLKSEL = REFCLK GT11_inst2REFCLK1GT11_inst3REFCLK1GT11CLK_inst2SYNCLK1OUTEN = DISABLESYNCLK2OUTEN = ENABLEREFCLKSEL = REFCLKREFCLK2REFCLK2REFCLK2GT11CLK input REFCLKdrives the entire columnvia the SYNCLK clock trees.GT11_inst1(MGTB of tile)GREFCLKGT11_inst2(MGTA of tile)GT11_inst3(MGTB of tile)GREFCLKGREFCLKNote: inst1 cannot share GREFCLKwith inst2 and inst3 without usingfabric clocking resources.UG076_CH2_06_050806Clock from GlobalClock Tree IncludingOther MGT ColumnClock from GlobalClock Tree IncludingOther MGT ColumnClock from GlobalClock Tree IncludingOther MGT ColumnClock from GlobalClock Tree IncludingOther MGT Column(a) (b)
