Virtex-4 RocketIO MGT User Guide www.xilinx.com 85UG076 (v4.1) November 2, 2008ResetsR• RX Buffer — RXUSRCLK and PCS RXCLK domains• Channel Bonding & Clock Correction Logic — RXUSRCLK and PCS RXCLK domains• Comma Detect Align — PCS RXCLK Domain• Digital CDRSee Figure 2-7, “PCS Receive Clocking Domains and Datapaths,” page 74 for PCS receiveclocking domains and datapaths.For Digital CDR, asserting RXRESET causes the PMA parallel clock RXRECCLK1 to stoptoggling (remain at a constant value).CRC ResetCRCRESET resets the CRC section of the transmitter (TXCRCRESET) and receiver(RXCRCRESET). (See Chapter 5, “Cyclic Redundancy Check (CRC).”)Proper assertion and deassertion of these resets are necessary to set up the CRC for use.Resetting the TransceiverThis section describes different use cases of resetting the transceiver.Transmit Reset Sequence: TX Buffer UsedFigure 2-14 provides a flow chart of the transmit reset sequence when the TX buffer isused. Refer to the following points in conjunction with this figure:• The flow chart uses TXUSRCLK as reference to the wait time for each state. Do not useTXUSRCLK as the clock source for this block; this clock might not be present duringsome states. Use a free-running clock (for example, the system's clock) and make surethat the wait time for each state equals the specified number of TXUSRCLK cycles.• It is assumed that the frequency of TXUSRCLK is slower than the frequency ofTXUSRCLK2. If TXUSRCLK2 is slower, use that clock as reference to the wait time foreach state.• tx_usrclk_stable is a status signal from the user's application that is asserted Highwhen both TXUSRCLK and TXUSRCLK2 clocks are stable. For example, if a DCM isused to generate both the TXUSRCLK and TXUSRCLK2 clocks, then the DCMLOCKED signal can be used here.• tx_pcs_reset_cnt is a counter from the user's application that is incremented everytime both TXBUFERR and TXLOCK signals are asserted. It is reset when the blockcycles back to the TX_PMA_RESET state.• In synchronous systems like the GPON application whereRXRECCLK1/RXRECCLK2 is used for the TX PLL, the TX_SYSTEM_RESET stateshould stall until there is a stable RXLOCK signal from the RX PLL (RXLOCK == 1 for16K [16 x 1024] REFCLK cycles). The condition in going from TX_SYSTEM_RESET toTX_PMA_RESET needs to be modified to:♦ Analog CDR Mode:!system_reset && (RXLOCK == 1 for 16K [16 x 1024] REFCLK cycles)♦ Digital CDR Mode:!system_reset && RXLOCK == 1See “RX Reset Sequence Background,” page 100 for information on the 16K REFCLK cyclesrequirement.
