Virtex-4 RocketIO MGT User Guide www.xilinx.com 153UG076 (v4.1) November 2, 2008RChapter 5Cyclic Redundancy Check (CRC)Each RocketIO MGT has two 32-bit CRC blocks. The input data path width can be 1 to 8bytes and can be changed on each clock cycle to allow the computation of a CRC of anydata length. The CRC initial value is set with the attribute RXCRCINITVAL, or theDynamic Reconfiguration Port. Figure 5-1 shows the basic concept of the 32-bit CRC block.Table 5-1 shows the ports and attributes associated with the 32-bit CRC block.Figure 5-1: 32-bit CRC Inputs and OutputsTable 5-1: Ports for the RX and TX CRC BlocksPort I/O Port Size FunctionRXCRCCLK I 1 Receiver CRC logic clock.RXCRCDATAVALID I 1 Signals that the RXCRCIN data is valid when setto logic 1.RXCRCDATAWIDTH I 3 Determines the data width of the RXCRCIN.RXCRCIN I 64Receiver CRC logic input data. See Table 5-4 fordata width and active data bus bits withRXDATA mapping.RXCRCINIT I 1 Initial value that the RX CRC uses to start theCRC calculation.RXCRCINTCLK I 1 Receiver CRC/FPGA fabric interface clock.RXCRCOUT O 32 Receiver CRC output data. This bus must beinverted to obtain the valid CRC value.RXCRCPD I 1 Powers down RX CRC Logic when set to logic 1.RXCRCRESET I 1 Resets the RX CRC logic when set to logic 1.TXCRCCLK I 1 Transmitter CRC logic clock.32-bit CRC CRCOUTCRCINCRCDATAWIDTHCRCINITVALCRCINITCRCCLKCRCINTCLKCRCRESETCRCPDCRCDATAVALID32ug076_ch3_05_12060564332
