224 www.xilinx.com Virtex-4 RocketIO MGT User GuideUG076 (v4.1) November 2, 2008Chapter 8: Low-Latency Design RRX Low Latency Buffer Bypass ModeOverviewFor this mode, the RX buffer is bypassed and RXSYNC must be used to synchronize thePCS RXCLK and PMA RXCLK0. The PCX RXCLK is used as the synchronization clocksource.ClockingIn this mode, only the internal PCS dividers can be used for RXUSRCLK. As a result, thismode is incompatible with channel bonding and 8-byte RX interface data path widths.• If 4-byte mode is required, RX_CLOCK_DIVIDER = 11• If 2-byte mode is required, RX_CLOCK_DIVIDER = 01• If 1-byte mode is required, RX_CLOCK_DIVIDER = 10As shown in Table 8-12, an external RXUSRCLK cannot be used in buffer-bypass mode.Where RXRECCLK1 is used as the source for RXUSRCLK and RXUSRCLK2, theasynchronous PMA clock dividers must be used. These dividers are not affected by thephase alignment circuit. Therefore, the phase alignment circuit adjusts the phase only ofPMA RXCLK0, not of RXRECCLK1. This configuration requires attributesRXCLKMODE[1] = 1, RXCLKMODE[4] = 0, and RXRECCLK1_USE_SYNC = FALSE.Table 8-12: RX Use Models: Low-Latency Buffer Bypass ModeUSE MODEL(1)RX_BUFFER_USERXUSRCLK SOURCEBYPASS MODE(4)PORTS ATTRIBUTESRXBLOCKSYNC64B66BUSERXCOMMADETUSERXDEC8B10BUSERXDEC64B66BUSE(1)RXDESCRAM64B66BUSERXSYNC(2)PMA_BIT_SLIPRXDATA_SELRXCLK0_FORCE_PMACLKRX_CLOCK_DIVIDER(1,3)RX_2AFALSEInternal PCSclock dividersto deriveRXUSRCLKfromRXUSRCLK2No Bypass. Uses 8B/10BDecode. 0 1 1 0 0REQ’D FALSE11FALSE11RX_2B Decoding Bypass of 8B/10Band 64B/66B Decode. 0 1 0 0 0 10 11RX_2C Full PCS Bypass, includingComma Detection block. 0 0 0 0 0 01 11Notes:1. All cases addressed assume a fabric width of 4 bytes. Refer to section “Clocking,” page 224 for 2 byte or 1 byte fabric width.2. RXSYNC functionality must be used in order to sync the PCS/PMA clocks.3. Because the internal PCS dividers are used, Parallel Loopback and Channel Bonding are not supported.4. 64B/66B encoding/decoding is not supported.
