200 www.xilinx.com Virtex-4 RocketIO MGT User GuideUG076 (v4.1) November 2, 2008Chapter 8: Low-Latency Design RTX Low Latency Buffered Mode with Channel DeskewOverviewFor this mode, the TXSYNC functionality is required to synchronize the PCS and PMAclocks across all channels that need to be deskewed.Transmitters in different MGT tiles are not inherently aligned, as their TX PMA parallelclocks are generated from independent PLLs. The phase alignment circuit aligns the phaseof the PMA parallel clocks in multiple transceivers, thus reducing the skew seen at theserial TX outputs.ClockingFigure 8-3 shows GREFCLK used as the synchronization clock. Since GREFCLK has anunknown phase relationship to the PCS TXCLK domain, the phase alignment circuit usingGREFCLK inherits the phase uncertainty and passes it to the TX PMA parallel clock (PMATXCLK0). The user must then source the PCS TXCLK with PMA TXCLK0 and use the TXbuffer to compensate for the phase difference between the TXUSRCLK and PCS TXCLKclock domains. The frequency of GREFCLK must be equal to or less than the frequency ofTXUSRCLK. At the same time, GREFCLK can be used as the TX PLL reference clock.The setting of TXABPMACLKSEL does not affect the operation of the phase alignmentcircuit. The phase alignment circuit adjusts the phase only of PMA TXCLK0 and notTXOUTCLK1 as long as TXOUTCLK1 is sourced from the asynchronous PMA clockdividers (not the synchronous dividers). If TXOUTCLK1 is to be used as the source forTXUSRCLK2 in Use Models TX_1x and TX_2x, the asynchronous PCS clock dividers mustbe used. These dividers are not affected by the phase alignment circuit. Doing this requiresattributes TXCLKMODE[0] = 0, TXCLKMODE[2] = 1, and TXOUTCLK1_USE_SYNC =FALSE.GREFCLK's limitation of 1 Gb/s does not apply if it is only being used as an alignmentreference. For data rates greater than 1 Gb/s, GREFCLK can be used as the alignmentreference and MGTCLK can be used as the TX PLL reference clock.Use Models TX_2A through TX_2D illustrate the use of internal PCS clock dividers,whereas Use Models TX_2E through TX_2H illustrate the use of an external clock to drivethe TXUSRCLK port.This function is recommended for standards such as SFI4.2, where there is a specifiedmaximum channel skew and no inherent channel bonding functionality.Figure 8-3: Using GREFCLK as Synchronization Clock (Use Models TX_2A-H)TXUSRCLK2Clock DomainTXUSRCLKClock DomainPCS TXCLKClock DomainTX RINGBUFFERPCSClockDividersPMA TXCLK0PhaseAlignGREFCLKPMA SyncClockDividersTXCLK0TXUSRCLK2TXUSRCLKug076_ch8_03_050906
