Virtex-4 RocketIO MGT User Guide www.xilinx.com 91UG076 (v4.1) November 2, 2008ResetsR• It is assumed that the frequency of TXUSRCLK is slower than the frequency ofTXUSRCLK2. If TXUSRCLK2 is slower, use that clock as reference to the wait time foreach state. An exception of this requirement is the wait time between assertions ofTXLOCK and TXSYNC signals, from TX_WAIT_LOCK to TX_SYNC states. Use thespecified TXUSRCLK2 in this step.• See Figure 8-15, “TXSYNC Timing,” page 214 regarding the 12,000 TXUSRCLK2cycles and the 64 synchronization clock cycles specified in this block.• tx_usrclk_stable is a status signal from the user's application that is asserted Highwhen both TXUSRCLK and TXUSRCLK2 clocks are stable. For example, if a DCM isFigure 2-17: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassedand tx_align_err Is Not Usedsystem_reset==0TX_SYSTEM_RESETTX_PMA_RESETTX_WAIT_PCSTX_WAIT_LOCKTXPMARESET==1 for3 TXUSRCLK cyclestx_usrclk_stable==1 && TXLOCK==1for 12,000 TXUSRCLK2 cyclesTXRESET==1 for3 TXUSRCLK cycles5 TXUSRCLK cyclesTXLOCK==0TX_SYNCTXLOCK==0TX_PCS_RESETTXLOCK==0TXSYNC==1 for64 synchronization clock cyclesTX_READYTXLOCK==0ug076_ch2_18_040406
