Virtex-4 RocketIO MGT User Guide www.xilinx.com 219UG076 (v4.1) November 2, 2008RX LatencyRRX LatencyTo minimize the latency in the RX, the phase discrepancy between the PCS RXCLK andPMA RXCLK0 can be minimized by the RX phase alignment circuitry. This allows the userto bypass portions of the PCS or the entire PCS and thereby reduce the latency through theRX side of the MGT.In cases where the RX buffer is bypassed, the phase alignment circuitry is necessary toalign the PCS RXCLK and PMA RXCLK0.The most frequently anticipated use cases are mentioned below. The user can use theseexamples as a guide to determine a custom path if required.RX Low Latency Buffered ModeOverviewFor this mode, the RXSYNC functionality is not required. This results in bypassedfunctionality without the need for synchronizing the PCS and PMA clocks.ClockingThere is no particular clocking restriction in this mode. If there are multiple synchronizedchannels, the same USRCLK and USRCLK2 should be input to all the MGTs so that theyare all in phase with each other.As noted earlier, if channel bonding is being used, the internal PCS dividers cannot beused, and an external RXUSRCLK must be provided.To use the internal PCS dividers for RXUSRCLK (do not use for channel bonding becausebonded GT11s must share the same RXUSRCLK):• If 4-byte mode is required, RX_CLOCK_DIVIDER = 11.• If 2-byte mode is required, RX_CLOCK_DIVIDER = 01.• If 1-byte mode is required, RX_CLOCK_DIVIDER = 10.• Set RXCLK0_FORCE_PMACLK to TRUE.To provide for an external RXUSRCLK:• Set RX_CLOCK_DIVIDER = 00 and provide the appropriate frequency clock at theRXUSRCLK port. This might require the use of an additional DCM or PMCD.• Set RXCLK0_FORCE_PMACLK to FALSE.
