Virtex-4 RocketIO MGT User Guide www.xilinx.com 103UG076 (v4.1) November 2, 2008Bus InterfaceRThe overflow mark is set when the difference between the write and read pointer is greaterthan 57 bytes. The underflow mark is set when the difference between the write and readpointer is less than 17 bytes. These cases are illustrated in Figure 3-4:An overflow or underflow on the RX ring buffer causes RXBUFERR to go High.Bus InterfaceExternal Bus Width Configuration (Fabric Interface)The fabric interface module resides in the PCS portion of the MGT. The PCS is divided intotransmit (TX) and receive (RX) blocks. Separate fabric interface blocks reside in TX and RXblocks.The PCS TX fabric interface is used to transform data from the fabric clock domain(TXUSRCLK2) to the internal PCS clock domain (TXUSRCLK). The internal PCS data pathis 4 bytes (32/40 bits) wide. The TX fabric interface aggregates user data if the fabric clockdomain is higher frequency (narrower bus width: one or two byte mode) than the internalclock domain. It distributes data if the fabric clock domain is slower (eight byte mode) thanthe internal clock domain. The RX fabric interface distributes user data if the fabric clockdomain is higher frequency (narrower bus width: one or two byte mode) than internalclock domain. It aggregates data if the fabric clock domain is slower (eight byte mode) thanthe internal clock domain.By using the signals TXDATAWIDTH[1:0] and RXDATAWIDTH[1:0], the fabric interfacecan be determined. This also determines the USRCLK and USRCLK2 relationships. Forslower serial speeds, 1-byte and 2-byte interfaces are preferred. For higher serial rates,4-byte and 8-byte interfaces are recommended.Table 3-2 shows the available external (fabric interface) bus width settings.Figure 3-4: RX Ring Buffer Overflow and UnderflowRX Ring Buffer32wr_ptr57(Bufferoverflowsat > 57)17(Bufferunderflowsat < 17)DataData6464RX Ring Buffer32wr_ptrrd_ptr rd_ptrug076_ch3_42_060107
