Virtex-4 RocketIO MGT User Guide www.xilinx.com 135UG076 (v4.1) November 2, 2008Digital ReceiverR• Digital receiver output clock = 1X clock = 124.4 ÷ 8 (sampling rate) = 15.55 Mhz (linerate/parallel data width)In addition to the 1X Clock, the digital receiver can also generate a 4X and 2X clock basedon the fabric interface width specified by the user. Table 3-26 defines the clock frequency touse for a given interface width. The parallel data is always frequency-locked and phase-locked to these clocks.Because the receiver is locked to reference, the inherent frequency difference between theincoming data and the local PLL clock must be accommodated. In the Virtex-4 RocketIOtransceiver, this is accomplished by modulating the recovered clock. Typically, therecovered clock is output to the FPGA fabric at the nominal frequency, but occasionally,shorter clock periods are generated. The length of the shorter periods depends on the datawidth chosen for the interface between the MGT and the FPGA logic. This is shown inTable 3-25.The FPGA logic driven by this clock must be able to run at the clock frequency determinedby the shorter period of the recovered clock.In the example given in Figure 3-23, the nominal frequency of the recovered clock is15.55 MHz. The normal clock period for this frequency is 64 ns; however, the 12.5% shorterclock period is 56 ns, which translates into a clock frequency of 17.9 MHz.This variation becomes more important at smaller interface widths and higher interfacespeeds. For example, changing to a 1-byte interface between MGT and FPGA inFigure 3-23 would result in a nominal speed of 62.2 MHz and period of 16 ns. The 25%shorter clock period (12 ns) translates into a recovered clock frequency of 83.3 MHz.Figure 3-23: Digital Receiver ExampleTable 3-25: Variation of Recovered Clock PeriodInterface Width(8x Oversampling)OutputClock RateClock PeriodVariation [%]Speed MarginRequired [%]1 Byte 4X 25 1332 Byte 2X 12.5 1144 Byte 1X 12.5 114PCS Digital CDR Rx PMARXP/RXN(0.622 Gb/s)PLL*Sample Processorand Data Tracking(8X Oversampling Mode)Parallel clockParallel clocklocked to data155.5 MHzReferenceClock32/40 bitparallel data32/40 bitparallel data* PLL configured to remainlocked to Reference Clock40-bit parallel data15.55 MHz2.488G CLK= 4.976 Gb/sSIPOug076_ch3_22_040706(four 8-bit/10-bit symbols)(124.4 MHz = 4.976G/40)
