Virtex-4 RocketIO MGT User Guide www.xilinx.com 63UG076 (v4.1) November 2, 2008Clock DistributionRThis chapter also includes several use models (see “Common Reference Clock UseModels,” page 66). The use models illustrated here represent the most commonconfigurations, but other configurations are also possible.GT11CLK_MGT and Reference Clock RoutingEach MGT tile contains a GT11CLK_MGT block implementable by instantiating either theGT11CLK or GT11CLK_MGT ports and attributes shown in Table 2-1.Note: The term GT11CLK_MGT block refers to the hardware, whereas GT11CLK_MGT moduleand GT11CLK module refer to the standard and advanced software primitives that access the block.If no specific reference is made to “block” or “module,” the user should assume “module” is intendedand refers to the software primitives.Each column must use its own dedicated MGTCLKP and MGTCLKN clock sourcesimplemented through the GT11CLK_MGT or GT11CLK module. MGTCLK signals cannotbe routed across the FPGA fabric, especially in designs where the data rate is 1 Gb/s orhigher, because excessive jitter results. MGTCLK source locations and package pinouts forthe various devices are shown in Table 7-6 through Table 7-10. To implement such aconnection, the GT11CLK_MGT should be instantiated. This is shown in Figure 2-2,page 66.In general, the GT11CLK_MGT module is always used. The GT11CLK module allowsmore clocking options for MGTs in a given column, including feeding the fabric clock treesvia SYNCLK1 and SYNCLK2 to the REFCLK1 and REFCLK2 column buses. Thiseliminates the need for individual connections through GREFCLK for multiple MGTs inthe same column.Table 2-1: MGTCLK Ports and AttributesGT11CLK GT11CLK_MGT I/O DescriptionPortsSYNCLK1OUT SYNCLK1OUT O This output drives the REFCLK1 column bus and the FPGAclock trees.SYNCLK2OUT SYNCLK2OUT O This output drives the REFCLK2 column bus and the FPGAclock trees.MGTCLKN MGTCLKN I This is the differential package input for the MGT column.MGTCLKP MGTCLKP IREFCLK N/A IThis input is from the FPGA fabric This reference clock shouldonly be used in sub-1 Gb/s operation. This allows a fabric clockto access the SYNCLK buses.RXBCLK N/A I Reserved. This clock port is not supported.SYNCLK1IN N/A I This input is connected to SYNCLK1OUT of an adjacentGT11CLK or GT11CLK_MGT.SYNCLK2IN N/A I This input is connected to SYNCLK2OUT of an adjacentGT11CLK or GT11CLK_MGT.AttributesREFCLKSEL N/A N/A Determines which clock input is used for the reference clock(MGTCLK, RXBCLK, REFCLK, SYNCLK1IN, SYNCLK2IN).
