228 www.xilinx.com Virtex-4 RocketIO MGT User GuideUG076 (v4.1) November 2, 2008Chapter 8: Low-Latency Design RRXSYNCOverviewThe PMA phase alignment block compares and then synchronizes the phase relationshipbetween PMA RXCLK0 and the PCS RXCLK. The phase alignment circuit is enabled by therising edge of the fabric port RXSYNC. RXSYNC is similar in functionality to TXSYNC.From assertion of RXSYNC, the phase alignment process takes two sweeps. A sweep isdefined here as the rising edges of the two parallel clocks that are compared crossing eachother in response to a high-speed serial clock being skipped. Two sweeps are done insteadof one to ensure that a glitch at startup (rising edge of RXSYNC) does not confuse thecircuit into thinking that the clocks are aligned when in reality they are not.Therefore, the first sweep is variable in length, depending on the initial relationship of thetwo clocks. The second sweep takes either 16 or 20 adjustments, according to thesynchronous clock divider setting (32-bit or 40-bit data path). The circuit adjusts one high-speed clock for every parallel clock being used as the timing reference (PCS RXCLK).The phase alignment process should be initiated only once the RX PLL is locked asindicated by the RXLOCK output. If for any reason the RX PLL becomes unlocked then thealignment process must be reinitiated.TimingFigure 8-22 illustrates the timing waveform of all the signals involved in the RX phasealignment process.Usage1. Phase alignment is a one-time multi-clock-cycle event enabled when the RXSYNC portis asserted. Although the RXSYNC port is asynchronous to RXUSRCLK2, the user cansimply generate RXSYNC in the RXUSRCLK2 domain and apply the RXSYNC signalto all MGTs involved in the RX phase alignment.Figure 8-22: RXSYNC TimingNote: PCS RXCLK and RXCLK0 are MGT internal signals, not MGT fabric ports.TSYNC_to_RSTTLOCK to SYNCTSYNCTRSTPCS RXCLKRXCLK0RXLOCKRXSYNCRXRESETPhase Alignment inProgressUG076_ch8_18_042606
