Virtex-4 RocketIO MGT User Guide www.xilinx.com 321UG076 (v4.1) November 2, 2008RAppendix DSpecial Analog FunctionsReceiver Sample Phase AdjustmentNote: The Receiver Sample Phase Adjustment function is for ADVANCED USERS ONLY andshould be used only after a complete understanding of the Receiver Sample Phase Adjustmentattributes has been attained. INCORRECT USE COULD RESULT IN UNDESIRABLE SYSTEMOPERATION. This functionality only applies for configurations in which the receiver is set in analogCDR mode or the PLL is set to lock to receiver data (RXDIGRX = FALSE).There are serial-link situations where sampling the data at the center of the eye (based onthe recovered clock) does not produce the best results. The MGT allows adjusting thephase of this sample point. This type of adjustment can be done dynamically, whichrequires that the Dynamic Reconfiguration Port (DRP) be used in conjunction with theRXSELDACFIX[4:0] and RXSELDACTRAN[4:0] registers. These registers (whose DRPaddresses are shown inTable D-1) can co-control the CDR phase up to ±46.9% UI in31 steps. Table D-2 shows the settings and how this correlates to UI phase adjustment.Table D-1: Register Address LocationRegister MGTA Address and Bits MGTB Address and BitsRXSELDACFIX[4] 0x56 bit [14] 0x72 bit [14]RXSELDACFIX[3:0] 0x46 bit [14:11] 0x62 bit [14:11]RXSELDACTRAN[4:0] 0x46 bit [10:6] 0x62 bit [10:6]Table D-2: Example RXSELDACTRAN and RXSELDACFIX CombinationsRXSELDACFIX value RXSELDACTRAN Value Phase Adjustment(in UI%)11111 00001 –46.87511110 00010 –43.75011101 00011 –40.62511100 00100 –37.50011011 00101 –34.37511010 00110 –31.25011001 00111 –28.12511000 01000 –25.00010111 01001 –21.87510110 01010 –18.750
