192 www.xilinx.com Virtex-4 RocketIO MGT User GuideUG076 (v4.1) November 2, 2008Chapter 8: Low-Latency Design RPCS Clocking Domains and Data PathsNote: In this chapter, all references to Unit Intervals (UI) are in relation to the serial bit time.ReceiverRefer to Figure 8-1. If the shortest path is taken, the RX latency is reduced to the latency ofthe RX SERDES (64 UI or 80 UI), PMA/PCS interface (two RXCLK0 cycles), and fabricinterface (one RXUSRCLK2 cycle and one RXUSRCLK cycle). Refer to Table 8-1, page 194.This results in a latency of less than seven RXUSRCLK2 cycles in the 4-byte mode.Figure 8-1: PCS Receive Clocking Domains and Data Paths13x64 bitRingBuffer8B/10BDecode10GBASE-RDecode (1)64B/66BDescram (1)Channel Bonding &Clock CorrectionClockControl10GBASE-RBlockSync(1)CommaDetectAlignSync Control LogicSIPOPCSDividers& PhaseAlignRXPRXNPMA PCSRXDATARXCHARISK...ETCRXUSRCLKRXRECCLK1/RXRECCLK2RXUSRCLK2RXBLOCKSYNC64B66BUSE,RXCOMMADETUSERXDEC8B10BUSE,RXDESCRAM64B66BUSE RX_BUFFER_USE RXDEC64B66BUSE,RXDATA_SELENMCOMMAALIGNENPCOMMAALIGN110100100100TF000100011010001RXUSRCLK RXUSRCLK2PCSRXCLK÷4÷200 11 01 101XXX 0100RXCLK0_FORCE_PMACLK, LOOPBACK[0],RX_CLOCK_DIVIDERX_CLOCK_DIVIDER0000 0X11 0X01 0X10PMA TXCLK0PMA RXCLK0Fabric Interfaceug076_ch8_01_061507Note: (1) 64B/66B encoding/decoding is not supported.
