Virtex-4 RocketIO MGT User Guide www.xilinx.com 95UG076 (v4.1) November 2, 2008ResetsR3. RX_WAIT_LOCK: Stall until RXLOCK is High and until the clocks on RXUSRCLKand RXUSRCLK2 are stable (rx_usrclk_stable == 1). In addition:♦ For Analog CDR mode, RX_WAIT_LOCK state should also stall until RXLOCK isHigh for 16K (16 x 1024) REFCLK cycles. See “RX Reset Sequence Background,”page 100 for information on the 16K REFCLK cycles requirement.♦ For Digital CDR mode, since the RX PLL is locked to the reference clock, there isno need to have RXLOCK be asserted High for a specific number of REFCLKcycles.RXPMARESET == 0RXRESET == X4. RX_PCS_RESET: Assert RXRESET for three RXUSRCLK cycles. If RXLOCK isdeasserted, go back to RX_WAIT_LOCK state.RXPMARESET == 0RXRESET == 15. RX_WAIT_PCS: Wait for five RXUSRCLK cycles after deassertion of RXRESET. IfRXLOCK is deasserted, go back to RX_WAIT_LOCK state.RXPMARESET == 0RXRESET == 06. RX_ALMOST_READY: Wait for 64 RXUSRCLK cycles with no error on the receiveddata and RXLOCK High for this amount of time. This is to ensure that the RX MGT isstable after start-up and ready for data reception. If RXLOCK is deasserted, go back toRX_WAIT_LOCK state. If there is an rx_error detected while RXLOCK is High, thereset sequence block should apply RXRESET by cycling back to the RX_PCS_RESETstate. If this step occurs 16 times as monitored by the rx_pcs_reset_cnt counter, apply aRXPMARESET by cycling back to the RX_PMA_RESET state.RXPMARESET == 0RXRESET == 07. RX_READY: Once rx_error is monitored Low for some time, the RX link is READY fordata reception.RXPMARESET == 0RXRESET == 0Figure 2-20 and Figure 2-21 show timing diagrams of resetting the receiver where the RXbuffer is used. Refer to Figure 2-19 for more details.Figure 2-20: Resetting the Receiver in Digital CDR Mode Where RX Buffer Is UsedRXUSRCLKRXLOCKRXRESETRXPMARESETRXBUFERROnce RX error is monitored Low for some time, RX Link is READYug076_ch2_21_040406
