Virtex-4 RocketIO MGT User Guide www.xilinx.com 123UG076 (v4.1) November 2, 2008Clock CorrectionRRXSLIDERXSLIDE allows manual control of the PCS barrel shifter for applications that require analignment function that cannot be defined with PCOMMA_32B_VALUE/MCOMMA_32B_VALUE. When RXSLIDE is set to a logic 1, the position of the barrelshifter can be adjusted by one bit. This data increment can continue until it reaches themost significant bit, equal to the maximum word length minus 1, where it rolls over.• RXSLIDE must be set to logic 1 for a minimum of one RXUSRCLK2 cycle for bit slip tooccur.• RXSLIDE must be set to logic 0 for a minimum of three RXUSRCLK2 cycles beforebeing set to logic 1 again.Every RXSLIDE pulse causes a bit slip from a lower bit to higher bit.RXSLIDE functionality is shown in Figure 3-18.Note: RXSYNC with the PCS_BIT_SLIP attribute is no longer recommended for the bit slip feature.RXSLIDE should be used instead.Clock CorrectionClock correction is needed when the rate that data is fed into the write side of the receivebuffer is either slower or faster than the rate that data is retrieved from the read side of thereceive buffer. The rate of write data entering the buffer is determined by the frequency ofRXRECCLK1/RXRECCLK2. The rate of read data retrieved from the read side of the bufferis determined by the frequency of RXUSRCLK.Append/Remove Idle Clock CorrectionWhen the attribute CLK_COR_SEQ_DROP is set Low and CLK_CORRECT_USE is setHigh, the Append/Remove Idle Clock Correction mode is enabled. The Append/RemoveIdle Clock Correction mode corrects for differing clock rates by finding clock correctionsequences in the bitstream, and then either appending or removing sequences at the pointwhere the sequences were found.Note: CLK_COR_SEQ_DROP, when set to TRUE, causes all matched clock correction sequencesto be dropped despite the status of the buffer, and no appending to the buffer is allowed, eventuallycausing the buffer to empty. CLK_COR_SEQ_DROP should ALWAYS be set to FALSE.Figure 3-18: RXSLIDE Timing WaveformRXUSRCLK2RXDATARXSLIDEDatapath_delay (1)1. Datapath_delay depends on what receiver functions are used.2. The receive data is continuously 0x00000004. The data changes are caused by the rising and falling edge of RXSLIDE.ug076_ch3_9c_0731070x00000004 0x00000008 0x00000010 0x00000020Notes:
