194 www.xilinx.com Virtex-4 RocketIO MGT User GuideUG076 (v4.1) November 2, 2008Chapter 8: Low-Latency Design RPCS Data Path LatencyThe relationship between USRCLK and USRCLK2 (both TX and RX) depends on severalfactors, including the fabric interface width and the serial standard used. Anotherimportant timing consideration is the clock delay for data to pass through the entire MGT.Table 8-1 and Table 8-2 show approximate clock cycles for the main PCS blocks. The cyclesdepend on the external parallel data bus width (shown) and the phase relationshipbetween the different clocks, adding a small uncertainty factor to this table.Table 8-1: Latency through Various Receiver Components/Processes(1,2)Receive Blocks 1 Byte 2 Byte 4 Byte 8 ByteRX SERDES 62 UI or 80 UIPMA_PCS Interface (3) 2 PCS RXCLKRX DATAAlignment (3)CommaDET/Align 3 PCS RXCLKBypass 1 PCS RXCLKDecoding (4) 8B/10B 2 PCS RXCLK64B/66B (7) 2 PCS RXCLKBypass (3) 1 PCS RXCLKRX Buffer (5) No ClockCorrection3 PCS RXCLK + RXUSRCLK (phase diff) + 8 RXUSRCLK Latency +1 RXUSRCLKClock CorrectionMin/Max Used(3 PCS RXCLK + 1 RXUSRCLK + CLK_COR_MIN_LAT/4) < latency< (3 PCS RXCLK + 1 RXUSRCLK + CLK_COR_MAX_LAT/4)64B/66B (7)Decode 2 RXUSRCLKBypass (3) 1 RXUSRCLKFabric Interface (6) 1 RXUSRCLK +4 RXUSRCLK21 RXUSRCLK +2 RXUSRCLK21 RXUSRCLK +1 RXUSRCLK22 RXUSRCLK +1 RXUSRCLK2Notes:1. See Chapter 5, “Cyclic Redundancy Check (CRC)” for more information on CRC Latency.2. Linear equalization does not affect the receiver latency.3. These delays include a registered data mux, which accounts for one clock of delay.4. Bypass is when RXDEC8B10BUSE and RXDEC64B66BUSE are both deasserted.5. Bypassed buffer accounts for one registered data mux = 1 RXUSRCLK, but must be equal to 1 RXCLK0to bypass buffer. (Only works reliably if RX low-latency buffer bypass mode is implemented.)6. Fabric interface has delays in both clock domains. Clock ratios are:a. 1-byte mode USRCLK2:USRCLK ratio = 4:1b. 2-byte mode USRCLK2:USRCLK ratio = 2:1c. 4-byte mode USRCLK2:USRCLK ratio = 1:1d. 8-byte mode USRCLK2:USRCLK ratio = 1:27. 64B/66B encoding/decoding is not supported.
