Virtex-4 RocketIO MGT User Guide www.xilinx.com 261UG076 (v4.1) November 2, 2008BGA Escape ExampleRthickness of 62 mil is required. Cable and board traces use most of the available lossbudget. Therefore, a solution is needed to keep the remaining transitions below 0.1 dB.At 3 GHz, an 8 mil diameter / 30 mil pitch via should be used. For the less expensiveconnector, the top line of the table predicts about –0.17 dB of IL. Note that Table 12-1, oralternatively Equation 12-1 through Equation 12-3, can be applied to the capacitance ofany transitions, not just to differential vias. Although the IL is still low, there could beassociated ISI from the larger capacitances, which should be a focus of more detailedcircuit simulations.Example 3:This example uses a very dense 125 mil thick daughtercard for a 3.125 Gb/s data rate. Thenew design is an upgrade of an existing backplane legacy design. Here, the one-half datarate is 1.5625 GHz, and Equation 12-1 through Equation 12-3 can be used to project theexcess capacitance from the 1 GHz data. Doing these calculations, acceptable vias are16 mil diameter/30 mil pitch with short stubs, or 12 mil diameter/35 mil pitch with longvias.BGA Escape ExampleThe MGT signal pairs are routed along the edges of the flip-chip BGA. A microstrip is usedto escape. When there is adequate spacing from the BGA, the optimized GSSG differentialvias are used to change layers, if needed. It is recommended that these vias be staggered, asshown in Figure 12-2, to minimize the formation of slots in the power and ground planes.The round BGA pads for the RocketIO signals present a small amount of capacitance to asolid PCB ground below. Therefore one consideration is to open a void in the ground planebelow the signal pads with the same diameter as the signal pads. However, simulationsshow that the void only removes 30 fF of capacitance.Also of interest is the breakout of SIO adjacent to MGT analog supply pins. As noted earlierin “SelectIO-to-MGT Crosstalk” in the Physical Requirements section of Chapter 6 theseSelectIO™ requirements, if not taken into consideration, can have an affect on MGTperformance. This impact occurs when SIO solder balls are adjacent to MGT analog supplyscrewballs and their corresponding PCB vias are adjacent as well, creating both a packageand board coupling mechanism. The screwballs, which are part of the package, offer someFigure 12-2: BGA Escape Design Exampleug076_c12_04_051006Outer row of BGA pinsStaggereddifferential vias
