Virtex-4 RocketIO MGT User Guide www.xilinx.com 93UG076 (v4.1) November 2, 2008ResetsR7. TX_READY: TX link is ready.TXPMARESET == 0TXRESET == 0TXSYNC == 0Figure 2-18 shows a timing diagram for resetting the transmitter when the TX buffer isbypassed. Refer to Figure 2-16 and Figure 2-17 for more details.Receive Reset Sequence: RX Buffer UsedFigure 2-19 provides a flow chart of the receive reset sequence when the RX buffer is used.Refer to the following points in conjunction with this figure:• The flow chart uses RXUSRCLK as reference to the wait time for each state. Do not useRXUSRCLK as the clock source for this block; this clock might not be present duringsome states. Use a free-running clock (for example, the system's clock) and make surethat the wait time for each state equals the specified number of RXUSRCLK cycles.• It is assumed that the frequency of RXUSRCLK is slower than the frequency ofRXUSRCLK2. If RXUSRCLK2 is slower, use that clock as reference to the wait time foreach state.• rx_usrclk_stable is a status signal from the user's application that is asserted Highwhen both RXUSRCLK and RXUSRCLK2 clocks are stable. For example, if a DCM isused to generate both the RXUSRCLK and RXUSRCLK2 clocks, then the DCMLOCKED signal can be used here.• rx_error is a status signal from the user's application that is asserted High to indicatethat there is either an RX buffer error (RXBUFERR==1) or a burst of errors on thereceived data (RXDISPERR and/or RXNOTINTABLE signals are asserted).• rx_pcs_reset_cnt is a counter from the user's application that is incremented everytime both the rx_error and RXLOCK signals are asserted. It is reset when the blockcycles back to the RX_PMA_RESET state.• See “RX Reset Sequence Background,” page 100 for information on the 16K REFCLKcycles requirement.Figure 2-18: Resetting the Transmitter Where TX Buffer Is BypassedTXUSRCLKTXLOCKTXRESETTXPMARESETTXSYNCOnce TX phase alignment error is monitored Low for some time, TX Link is READYug076_ch2_19_040606
