Virtex-4 RocketIO MGT User Guide www.xilinx.com 215UG076 (v4.1) November 2, 2008TX Channel Skew using TXSYNCRc. If multiple TXSYNC pulses are necessary, it is also recommended that they bespaced at least four synchronization clock cycles apart.d. If TXSYNC is left asserted, it acts as an enable, such that if the PMA TXCLK0 edgeis detected prior to the synchronization clock, and TXSYNC is High, a clockadjustment is executed, dropping one high-speed serial clock (and the associateddata). Bringing TXSYNC Low causes the circuit to stay locked in its currentposition; therefore, after alignment is complete, TXSYNC should be brought Low.4. Finally, the PCS reset (TXRESET) must be asserted on all MGTs involved in the phasealignment to reset all TX buffer pointers. Aligning TXRESET to all transceivers isessential where the TX buffer is used and channel-to-channel skew needs to beminimized.a. The interval between TXSYNC deasserting and TXRESET asserting(TSYNC_to_RST) can be as small as zero TXUSRCLK2 cycles.b. The TXRESET pulse (TRST) normally should be synchronized to the TXUSRCLKdomain and should remain asserted for at least three TXUSRCLK cycles.Refer to section “Resets” in Chapter 2 for more details.5. MGTA/MGTB Register 0x43[7] = 1 always for TX low latency. This can beaccomplished with a read-modify-write operation via the dynamic reconfigurationport. Alternatively, this can be achieved by adding the constraintTXCLK0_INVERT_PMALEAF = TRUE to the UCF file. The CORE Generator RocketIOWizard generates this constraint when choosing to bypass the buffer to enable lowlatency.TX Channel Skew using TXSYNCWorst-Case TX Skew EstimationSynchronization Clock = PCS TXCLK, TXPHASESEL = TRUEwhere:Skew TXSYNC Algnmt is the worst-case skew from the TXSYNC alignment circuit. This is 2 UIbecause the PMA-generated parallel clock (PMA TXCLK0) aligns from 0–2 UI ahead of theparallel clock used as a timing reference (PCS TXCLK or GREFCLK).Skew ClkRef is the worst-case clock skew across the FPGA for the alignment reference(synchronization clock), 100 ps worst case.Skew MGTClkRtng is the worst-case clock routing skew between the A and B MGTs, 320 psworst case.Skew USRCLKDiv is the skew from the internal USRCLK dividers. In the worst case, it is oneUSRCLK period for 1-byte and 2-byte fabric widths if the internal PCS dividers are used.This is because the phase relationship of the internal PCS dividers is asynchronousbetween MGTs. For 4-byte fabric width, there is no divider, so the skew is 0. For 2-byte and1-byte mode, the skew in UI depends on the internal datapath used:TXSkew worstcase UI( ) Skew TXSYNC Algnmt Skew ClkRef Skew MGTClkRtng Skew USRCLKDiv Skew Pkg+ + + +=2UI 100 psUI UserDataRate (ps)--------------------------------------------UI 320 psUI UserDataRate (ps)--------------------------------------------UI 0,16,20,24,30 UI( ) ~70 psUI UserDataRate (ps)--------------------------------------------UI+ + + +=
