Virtex-4 RocketIO MGT User Guide www.xilinx.com 201UG076 (v4.1) November 2, 2008Transmit Latency and Output SkewRUse ModelsTable 8-8: TX Use Models: Low-Latency Buffered Mode with Channel DeskewUSE MODEL(1)TX_BUFFER_USETXUSRCLK SOURCE(2)BYPASS MODE(5)PORTS ATTRIBUTESTXENC8B10BUSETXENC64B66BUSETXSCRAM64B66BUSE(3)TXGEARBOX64B66BUSE(3)TXSYNCTXDATA_SELTXCLK0_FORCE_PMACLKTX_CLOCK_DIVIDER(1)TXPHASESELTX_2ATRUEInternal PCS clockdividers to deriveTXUSRCLK fromTXUSRCLK2No Bypass. 10GBASE-REncode and 64B/66BGearBox and Scrambler0 1 1 1REQ’D 00 TRUE 11 FALSE(Note 4)TX_2B No Bypass. 8B/10B Encode 1 0 0 0TX_2C 64B/66B GearBox andScrambler Bypass 0 1 0 0TX_2D 8B/10B and 64B/66BEncoding Bypass 0 0 0 0TX_2ETRUE External TXUSRCLKNo Bypass. 10GBASE-REncode and 64B/66BGearBox and Scrambler0 1 1 1REQ’D 00FALSEorTRUE00 FALSE(Note 4)TX_2F No Bypass. 8B/10B Encode 1 0 0 0TX_2G 64B/66B GearBox andScrambler Bypass 0 1 0 0TX_2H 8B/10B and 64B/66BEncoding Bypass 0 0 0 0Notes:1. All cases addressed assume a fabric width of 4 bytes.a. For Use Models TX_2A -D, if 2-byte mode is required, TX_CLOCK_DIVIDER = 01.b. For Use Models TX_2A -D, if 1-byte mode is required, TX_CLOCK_DIVIDER = 10.c. For Use Models TX_2E-H, the appropriate frequency clock should be provided at the TXUSRCLK port for 2-byte or 1-byte mode.This could require the use of an additional DCM or PMCD.2. GREFCLK is used as clock synchronization source.3. TXSCRAM64B66BUSE and TXGEARBOX64B66BUSE are always to be set to the same value.4. MGTA/MGTB Register 0x43[7]=1 always for TX Low Latency. This can be accomplished with a Read-Modify-Write Operationvia the Dynamic Reconfiguration Port. Alternatively, this can be achieved by adding the constraint TXCLK0_INVERT_PMALEAF ="TRUE" to the UCF file. The COREGen RocketIO Wizard generates this constraint when choosing to bypass the buffer to enable LowLatency.5. 64B/66B encoding/decoding is not supported.
