000ttt1InIntegrationt intt DelayOuttReset tResettResetIEC13000177-2-en.vsdIEC13000177 V2 ENFigure 407: The next IN pulse is received before tReset has elapsed. Sufficienttime during the pulses is accumulated to reach tDelay. When tDelay isreached, OUT is set until tReset time has elapsed, which resets tDelayand OUT.tint integration timetReset time delay to resettDelay time delay to operateTable 606:TIGAPC technical dataFunction Cycle time (ms) Range of value AccuracyTime integrationcontinuous active 3 0-999999.99 s±0.2% or ±20 ms whichever isgreaterTime integrationcontinuous active8 0-999999.99 s ± 0.2% or ±50 ms whichever isgreaterTime integrationcontinuous active100 0-999999.99 s ±0.2% or ±250 ms whicheveris greaterTable 607:Number of TIGAPC instancesFunction Quantity with cycle time3 ms 8 ms 100 msTIGAPC - 30 -15.15 Elapsed time integrator with limit transgression andoverflow supervision TEIGAPC15.15.1 IdentificationFunction Description IEC 61850identificationIEC 60617identificationANSI/IEEE C37.2 devicenumberElapsed time integrator TEIGAPC - -1MRK502052-UEN B Section 15Logic851Technical manual
