NXP Semiconductors MPC5606S manuals
MPC5606S
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- Table Of Contents
- Introduction
- MPC5606S family comparison
- Block diagram
- Feature details
- e200z0h core processor
- Crossbar switch (XBAR)
- Enhanced Direct Memory Access (eDMA)
- Interrupt Controller (INTC)
- System Integration Unit (SIU)
- SRAM
- Enhanced Modular Input/Output System (eMIOS)
- Analog-to-Digital Converter (ADC)
- Deserial Serial Peripheral Interface (DSPI)
- FlexCAN
- Serial communication interface module (LINFlex)
- Periodic Interrupt Timer module (PIT)
- Real Time Counter (RTC)
- Parallel Data Interface (PDI)
- Liquid Crystal Display (LCD) driver
- Stepper Motor Controller (SMC)
- IEEE 1149.1 JTAG Controller (JTAGC)
- How to use the MPC5606S documents
- Using the MPC5606S
- Software design
- Input/output pins
- Chapter 2
- Memory Map
- Package pinouts
- Pad configuration during reset phases
- Pad types
- System pins
- Functional ports
- Signal details
- Register protection
- Modes of operation
- Register description
- Functional description
- Access errors
- Features
- External signal description
- SWT Interrupt Register (SWT_IR)
- SWT Timeout Register (SWT_TO)
- SWT Window Register (SWT_WN)
- SWT Counter Output Register (SWT_CO)
- Overview
- Device-specific implementation
- Normal conversion operating modes
- Injected channel conversion
- Abort conversion
- Analog clock generator and conversion timings
- Programmable analog watchdog
- DMA functionality
- External decode signals delay
- Register descriptions
- Control logic registers
- Main Status Register (MSR)
- Interrupt registers
- Channel Pending Registers (CEOCFR[1..2])
- Interrupt Mask Register (IMR)
- Channel Interrupt Mask Register (CIMR[1..2])
- Watchdog Threshold Interrupt Status Register (WTISR)
- Watchdog Threshold Interrupt Mask Register (WTIMR)
- DMA registers
- DMA Channel Select Register (DMAR[1..2])
- Threshold registers
- Threshold Register (THRHLR[0:3])
- Conversion timing registers CTR[1..2]
- Mask registers
- Injected Conversion Mask Registers (JCMR[1..2])
- Delay registers
- Data registers
- Reset Configuration Half Word Source (RCHW)
- Single-chip boot mode
- Boot and alternate boot
- BAM software flow
- BAM resources
- Download and execute the new code
- Download start address, VLE bit and code size
- Download data
- Boot from UART
- Bootstrap with CAN
- Protocol
- Interrupts
- Main features
- CAN Sampler Sample Registers 0–11
- Enabling/disabling the CAN Sampler
- Baud rate generation
- Clock architecture
- Auxiliary clocks
- Clock gating
- Clock Generation Module (MC_CGM)
- Output clock multiplexing
- FXOSC external oscillator
- KHz OSC digital interface
- SIRC digital interface
- Modulation Register (MR)
- Normal mode with frequency modulation
- Powerdown mode
- Clock Monitor Unit (CMU)
- Crystal clock monitor
- Memory map and register description
- Control Status Register (CMU_CSR)
- Frequency Display Register (CMU_FDR)
- Low Frequency Reference Register FMPLL0 (CMU_LFREFR)
- Measurement Duration Register (CMU_MDR)
- Device-specific information
- eMIOS clocking configuration
- Unified Channel block
- Unified Channel memory map
- eMIOS200 Global FLAG Register (EMIOSGFLAG)
- eMIOS200 Output Update Disable (EMIOSOUDIS)
- eMIOS200 Disable Channel (EMIOSUCDIS)
- eMIOS200 UC A Register (EMIOSA[n])
- eMIOS200 UC B Register (EMIOSB[n])
- eMIOS200 UC Counter Register (EMIOSCNT[n])
- eMIOS200 UC Status Register (EMIOSS[n])
- Unified Channel (UC)
- UC modes of operation
- Input Programmable Filter (IPF)
- Clock Prescaler (CP)
- Effect of Freeze on the Unified Channel
- Effect of Freeze on the GCP
- Coherent accesses
- General operation
- Slave ports
- Slave mode
- Signal names and descriptions
- DSPI Transfer Count Register (DSPIx_TCR)
- DSPI Status Register (DSPIx_SR)
- DSPI PUSH TX FIFO Register (DSPIx_PUSHR)
- DSPI POP RX FIFO Register (DSPIx_POPR)
- DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn)
- Serial Peripheral Interface (SPI) configuration
- SPI Master mode
- Receive First In First Out (RX FIFO) buffering mechanism
- DSPI baud rate and clock delay generation
- Baud rate generator
- Transfer formats
- Classic SPI transfer format (CPHA = 0)
- Classic SPI transfer format (CPHA = 1)
- Modified SPI transfer format (MTFE = 1, CPHA = 0)
- Modified SPI transfer format (MTFE = 1, CPHA = 1)
- Continuous selection format
- Clock polarity switching between DSPI transfers
- Continuous serial communications clock
- Interrupts/DMA requests
- Transmit FIFO underflow interrupt request (TFUF)
- Module Disable mode
- Baud rate settings
- Delay settings
- Detailed signal descriptions
- Memory map and register definition
- Register summary
- Control Descriptor L0_2 Register
- Control Descriptor L0_3 Register
- Control Descriptor L0_4 Register
- Control Descriptor L0_5 Register
- Control Descriptor L0_6 Register
- Control Descriptor L0_7 Register
- Control Descriptor Cursor 2 Register (CtrlDescCursor_2)
- Control Descriptor Cursor 3 Register (CtrlDescCursor_3)
- DCU Mode Register (DCU_MODE)
- BGND Register
- DISP_SIZE Register
- HSYN_PARA Register
- SYN_POL Register
- Threshold Register
- Interrupt Status Register (INT_STATUS)
- Interrupt Mask Register (INT_MASK)
- COLBAR Registers
- Divide Ratio (DIV_RATIO) register
- SIGN_CALC_1 Register
- SIGN_CALC_2 Register
- PDI Status Register
- PDI Status Mask Register
- Parameter Error Status (PARR_ERR) register
- Mask PARR_ERR Status register
- THRESHOLD_INP_BUF_1 Register
- LUMA Component Register
- Red Chroma Components
- Blue Chroma Component Register
- CRC_POS Register
- FG0_bcolor
- Global Protection Register
- Soft Lock Bit Register L0
- Soft Lock Bit Register L1
- Soft Lock DISP_SIZE Register
- Soft Lock HSYNC/VSYNC PARA Register
- Soft Lock POL Register
- Soft Lock L1_TRANSP Register
- TFT LCD panel configuration
- DCU mode selection and background color
- Layer configuration and blending
- Control Descriptors
- Graphics and data format
- Alpha and Chroma-key blending
- 16 Freescale Semiconductor
- Transparency mode and blending
- Luminance mode
- Hardware cursor
- CLUT/Tile RAM
- Gamma correction
- Synchronizing to panel frame rate
- Error detection
- List of protected registers
- CRC area description
- Programming for Debug mode
- ITU-R BT.656 sync information extraction
- PDI interface description
- PDI interaction with other modules
- Modes of operation based on sync extraction
- Mode of operation depending on PDI_datain
- PDI-related interrupts
- Glossary
- DMA channels with no triggering capability
- Initialization/application information
- Enabling a source without periodic triggering
- Disabling a source
- Microarchitecture summary
- Integer unit features
- Unimplemented SPRs and Read-only SPRs
- Information specific to this device
- Memory map/register definition
- DMA Error Status (DMAES) register
- DMA Enable Request (DMAERQH, DMAERQL) registers
- DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) registers
- DMA Set Enable Request (DMASERQ) register
- DMA Clear Enable Request (DMACERQ) register
- DMA Clear Enable Error Interrupt (DMACEEI) register
- DMA Clear Interrupt Request (DMACINT) register
- DMA Set START Bit (DMASSRT) register
- DMA Interrupt Request (DMAINTH, DMAINTL) registers
- DMA Error (DMAERRH, DMAERRL) registers
- DMA Hardware Request Status (DMAHRSH, DMAHRSL) registers
- DMA General Purpose Output Register (DMAGPOR) register
- DMA Channel n Priority (DCHPRIn), n = 0,..., {15,31,63} registers
- Transfer Control Descriptor (TCD)
- DMA basic data flow
- DMA performance
- DMA programming errors
- DMA arbitration mode considerations
- Fixed group arbitration, round-robin channel arbitration
- Multiple requests
- TCD status
- Preemption status
- Dynamic programming
- Hardware request release timing
- Processor Core Type (PCT) register
- Miscellaneous Wakeup Control Register (MWCR)
- Miscellaneous Interrupt Register (MIR)
- Miscellaneous User-Defined Control Register (MUDCR)
- ECC registers
- ECC Status Register (ESR)
- ECC Error Generation Register (EEGR)
- Flash ECC Address Register (FEAR)
- Flash ECC Master Number Register (FEMR)
- Flash ECC Data Register (FEDR)
- RAM ECC Address Register (REAR)
- RAM ECC Master Number Register (REMR)
- RAM ECC Data Register (REDR)
- High-priority enables
- Flash module sectorization
- User mode operation
- Reset
- Power-Down mode
- Module Configuration Register (MCR)
- Low/Mid Address Space Block Locking Register (LML)
- 17.2.6.3 Non-Volatile Low/Mid Address Space Block Locking Register (NVLML
- High Address Space Block Locking Register (HBL)
- Secondary Low/Mid Address Space Block Locking Register (SLL)
- Low/Mid aDdress Space Block Select Register (LMS)
- High Address Space Block Select Register (HBS)
- Address Register (ADR)
- Bus Interface Unit 0 register (BIU0)
- Bus Interface Unit 2 register (BIU2)
- User Test 0 register (UT0)
- User Test 1 register (UT1)
- User Test 2 register (UT2)
- User Multiple Input Signature Register 1 (UMISR1)
- User Multiple Input Signature Register 2 (UMISR2)
- User Multiple Input Signature Register 4 (UMISR4)
- Non-volatile private censorship PassWord 0 register (NVPWD0)
- Non-Volatile Private Censorship Password 1 Register (NVPWD1)
- Non-Volatile System Censoring Information 1 register (NVSCI1)
- Non-Volatile User Options register (NVUSRO)
- Programming considerations
- Error Correction Code (ECC)
- 17.3.6.3 Non-Volatile Low/Mid Address Space Block Locking Register (NVLML
- User Multiple Input Signature Register 0 (UMISR0)
- User Multiple Input Signature Register 3 (UMISR3)
- Double Word program
- Sector erase
- User Test mode
- EEPROM emulation
- Censored mode
- Access protections
- Read cycles—buffer hit
- Access pipelining
- Bank1 temporary holding registers
- Read-While-Write functionality
- Wait-State emulation
- Timing diagrams
- Initialization / application information
- Flash memory setting recommendations
- FlexCAN module features
- Signal descriptions
- Message Buffer structure
- Rx FIFO Structure
- Control Register (CTRL)
- Free Running Timer (TIMER)
- Rx Global Mask (RXGMASK)
- Rx 14 Mask (RX14MASK)
- Error and Status Register (ESR)
- Interrupt Mask Register High (IMRH)
- Interrupt Mask Register Low (IMRL)
- Interrupt Flag Register High (IFRH)
- Rx Individual Mask Registers (RXIMR0–RXIMR63)
- Transmit process
- Receive process
- Matching process
- Data coherence
- Message Buffer deactivation
- Rx FIFO
- CAN protocol related features
- Overload frames
- Arbitration and matching timing
- Modes of operation: details
- FlexCAN Addressing and RAM size configurations
- Bypass mode
- Instruction register
- Boundary Scan register
- TAP Controller state machine
- Selecting an IEEE 1149.1-2001 register
- BYPASS instruction
- IDCODE instruction
- e200z0 OnCE controller
- e200z0 OnCE controller register description
- START Signal
- Slave Address Transmission
- Repeated START Signal
- Handshaking
- Generation of stop
- Generation of repeated START
- DMA application information
- Software vector mode
- Stop mode
- INTC Module Configuration Register (INTC_MCR)
- INTC Interrupt Acknowledge Register (INTC_IACKR)
- INTC End-of-Interrupt Register (INTC_EOIR)
- Interrupt Request Sources
- Peripheral Interrupt Requests
- Last-In First-Out (LIFO)
- Handshaking with processor
- Hardware vector mode handshaking
- ISR, RTOS, and task hierarchy
- Order of execution
- Priority Ceiling Protocol
- Software configurable interrupt requests
- Scheduling an ISR on another processor
- Proper setting of interrupt request priority
- LCD Prescaler Control Register (LCDPCR)
- LCD Contrast Control Register (LCDCCR)
- LCD Frontplane Enable Register 0 (FPENR0)
- LCD Frontplane Enable Register 1 (FPENR1)
- LCDRAM (Location 0)
- LCDRAM (Location 1)
- LCDRAM (Location 2)
- LCDRAM (Location 3)
- LCDRAM (Location 4)
- LCDRAM (Location 5)
- LCDRAM (Location 6)
- LCDRAM (Location 7)
- LCDRAM (Location 8)
- LCDRAM (Location 9)
- LCDRAM (Location 10)
- LCDRAM (Location 11)
- LCDRAM (Location 12)
- LCDRAM (Location 13)
- LCDRAM (Location 14)
- LCDRAM (Location 15)
- LCD clock and frame frequency
- Contrast adjustment
- LCD RAM
- LCD bias and modes of operation
- Operation in power saving modes
- Boost at switching
- LCD waveform examples
- duty multiplexed with 1/2 Bias mode
- Duty multiplexed with 1/3 Bias mode
- Duty multiplexed with 1/3 Bias
- Initialization information
- Features common to LIN and UART
- Fractional baud rate generation
- Operating modes
- Low-power mode (Sleep)
- Memory map and registers description
- LIN control register 1 (LINCR1)
- LIN interrupt enable register (LINIER)
- LIN status register (LINSR)
- LIN error status register (LINESR)
- UART mode control register (UARTCR)
- UART mode status register (UARTSR)
- LIN timeout control status register (LINTCSR)
- LIN output compare register (LINOCR)
- LIN fractional baud rate register (LINFBRR)
- LIN integer baud rate register (LINIBRR)
- LIN checksum field register (LINCFR)
- Buffer identifier register (BIDR)
- Buffer data register LSB (BDRL)
- Identifier filter enable register (IFER)
- Identifier filter match index (IFMI)
- Identifier filter mode register (IFMR)
- Identifier filter control register (IFCR2n)
- Identifier filter control register (IFCR2n + 1)
- Register map and reset values
- UART mode
- UART transmitter
- Slave mode with identifier filtering
- Slave mode with automatic resynchronization
- Output compare mode
- MPU Error Address Register, Slave Port n (MPU_EARn)
- MPU Error Detail Register, Slave Port n (MPU_EDRn)
- MPU Region Descriptor n (MPU_RGDn)
- 24.2.2.5 MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn
- Access evaluation—hit determination
- Putting It All Together and AHB Error Terminations
- Mode Control Register (ME_MCTL)
- Mode Enable Register (ME_ME)
- Interrupt Status Register (ME_IS)
- Interrupt Mask Register (ME_IM)
- Invalid Mode Transition Status Register (ME_IMTS)
- Debug Mode Transition Status Register (ME_DMTS)
- Reset Mode Configuration Register (ME_RESET_MC)
- Test Mode Configuration Register (ME_TEST_MC)
- DRUN Mode Configuration Register (ME_DRUN_MC)
- Run0...3 Mode Configuration Registers (ME_RUN0...3_MC)
- Stop Mode Configuration Register (ME_STOP_MC)
- Peripheral Status Register 0 (ME_PS0)
- Peripheral Status Register 1 (ME_PS1)
- Peripheral Status Register 2 (ME_PS2)
- Run Peripheral Configuration Registers (ME_RUN_PC0...7)
- Low-Power Peripheral Configuration Registers (ME_LP_PC0...7)
- Peripheral Control Registers (ME_PCTL0...143)
- Mode details
- Test mode
- Run0...3 modes
- Standby mode
- Target mode request
- Peripheral Clocks Disable
- Processor Low-Power mode entry
- Flash Modules Switch-On
- Peripheral Clocks Enable
- Power Domain #2 Switch-Off
- FMPLL0 Switch-Off
- Current mode update
- Protection of mode configuration registers
- Safe mode transition interrupt
- Application Example
- Operating mode
- Port Configuration Register (PCR)
- Development Control Register 1, 2 (DC1, DC2)
- Development Status Register (DS)
- Read/Write Access Control/Status (RWCS)
- Read/Write Access Address (RWA)
- Watchpoint Trigger Register (WT)
- Enabling Nexus clients for TAP access
- Configuring the NDI for Nexus messaging
- Nexus messaging
- Signal description
- Current Timer Value (CVAL) register
- Timer Control (TCTRL) register
- Debug mode
- Read Cycles
- Power Domain #1 Configuration Register (PCU_PCONF1)
- Power Domain Status Register (PCU_PSTAT)
- Mode transitions
- Standby mode transition
- Power saving for memories during Standby mode
- Preface
- Glossary for QuadSPI module
- QuadSPI modes of operation
- Debug mode (SPI modes only)
- Detailed Signal Description
- QSPI_IO2—QuadSPI Data IO_2
- AMBA bus register memory map
- IP bus register descriptions
- Transfer Count Register (QSPI_TCR)
- SPI Status Register (QSPI_SPISR)
- PUSH TX FIFO Register (QSPI_PUSHR)
- POP RX FIFO Register (QSPI_POPR)
- Transmit FIFO Registers 0 – 14 (QSPI_TXFR0 – QSPI_TXFR14)
- RX FIFO Registers 0 – 14 (QSPI_RXFR0 – QSPI_RXFR14)
- Instruction Code Register (QSPI_ICR)
- Sampling Register (QSPI_SMPR)
- RX Buffer Status Register (QSPI_RBSR)
- RX Buffer Data Registers 0–14 (QSPI_RBDR0–QSPI_RBDR14)
- TX Buffer Status Register (QSPI_TBSR)
- TX Buffer Data Register (QSPI_TBDR)
- Serial Flash Mode Status Register (QSPI_SFMSR)
- Serial Flash Mode Flag Register (QSPI_SFMFR)
- AHB bus register memory map descriptions
- AHB bus access considerations
- SPI (Serial Peripheral Interface) modes
- Start and Stop of SPI Transfers
- Master mode
- Baud Rate and Clock Delay Generation
- SPI Transfer Formats
- SPI mode interrupt and DMA requests
- SFM (Serial Flash) mode
- Issuing SFM Commands
- Flash Programming
- Byte Ordering of Serial Flash Data
- Serial Flash mode interrupt and DMA requests
- TX Buffer Operation
- Power saving features
- Leaving power-saving modes
- Baud rate settings—SPI modes only
- Delay settings—SPI modes only
- Oak family compatibility with the QuadSPI—SPI modes only
- Calculation of FIFO pointer addresses—SPI modes only
- 30.6.5.1 Address Calculation for the First-in Entry and Last-in Entry in the TX FIFO
- Available status/flag information—SFM mode only
- Overview of error flags
- DMA usage
- Serial Flash Devices
- Supported Instruction Codes in Winbond Devices
- Serial Flash Clock Frequency Limitations
- Functional Event Status Register (RGM_FES)
- Destructive Event Status Register (RGM_DES)
- Functional Event Reset Disable Register (RGM_FERD)
- Destructive Event Reset Disable Register (RGM_DERD)
- Functional Event Alternate Request Register (RGM_FEAR)
- Destructive Event Alternate Request Register (RGM_DEAR)
- Functional Event Short Sequence Register (RGM_FESS)
- Standby Reset Sequence Register (RGM_STDBY)
- Phase0 Phase
- Phase1 Phase
- Destructive Resets
- Functional Resets
- Alternate Event Generation
- Device specific information
- Debug support
- RTC Control Register (RTCC)
- RTC Status Register (RTCS)
- RTC Counter Register (RTCCNT)
- API functional description
- Register memory map
- Reset effects on SRAM accesses
- Initialization and application information
- SOUND_DURATION register
- SGL_STATUS register
- PWM alignment modes
- M1C0M/M1C0P/M1C1M/M1C1P — PWM output pins for Motor 1
- Motor Controller Control Register 0 (MCCTL0)
- Motor Controller Control Register 1 (MCCTL1)
- Motor Controller Period Register (MCPER)
- Motor Controller Duty Cycle Register (MCDC0..11)
- Short-circuit Detector Timeout Register (MCSDTO)
- Short-circuit Detector Enable Register 1 (MCSDE1)
- Short-circuit Detector Interrupt Enable Register 0 (MCSDIEN0)
- Short-circuit Detector Interrupt Enable Register 2 (MCSDIEN2)
- Short-circuit Detector Interrupt Register 1 (MCSDI1)
- and PWM mode functions
- PWM Duty Cycle
- Output switching delay
- Interrupt Enable and Flag Register (IRQ)
- Integration Accumulator Register (ITGACC)
- Blanking Counter Load Register (BLNCNTLD)
- SSD Prescale and Divider Register (PRESCALE)
- Analog Wrapper + Port Control
- Register Interface
- BIS control
- Stepper Stall Detection Measurement
- Details of the SSD Measurement
- Additional modes of operation
- SSD startup
- Setting of the PRESCALE Register
- Offset Cancellation Considerations
- Stepper Motor Transition Considerations
- Legacy modes—separate blanking and integration phase
- MCU ID Register #2 (MIDR2)
- Interrupt Status Flag Register (ISR)
- Interrupt Rising-Edge Event Enable Register (IREER)
- Interrupt Filter Enable Register (IFER)
- GPIO Pad Data Output Registers (GPDO0_3–GPDO132_135)
- Parallel GPIO Pad Data Out Registers (PGPDO0–PGPDO4)
- Parallel GPIO Pad Data In Register (PGPDI0–PGPDI4)
- Interrupt Filter Maximum Counter Registers (IFMC0–IFMC15)
- External interrupts
- External interrupt management
- System Status Register (STATUS)
- Error Configuration
- Debug Status Port Register
- Password Comparison Registers
- STM Count Register (STM_CNT)
- STM Channel Control Register (STM_CCRn)
- STM Channel Compare Register (STM_CMPn)
- VREG digital interface
- GPIO power supply configuration
- Power domain organization
- NMI Configuration Register (NCR)
- Wakeup/Interrupt Status Flag Register (WISR)
- Interrupt Request Enable Register (IRER)
- Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER)
- Wakeup/Interrupt Pullup Enable Register (WIPUER)
- NMI Management
- External Wakeups/Interrupts
- On-Chip Wakeups
- Appendix A
- Registers Under Protection
- Appendix B
- Register Map
- C.1 Changes between revisions 6 and 7
- C.2 Changes between revisions 5 and 6
- C.3 Changes between revisions 4 and 5
- C.4 Changes between revisions 3 and 4
- C.5 Changes between revisions 2 and 3
- C.6 Changes between revisions 1 and 2
- C.7 Changes between revisions 0 and 1
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