Deserial Serial Peripheral Interface (DSPI)MPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 323When the CONT = 1 and the CS signal for the next transfer is the same as for the current transfer, the CSsignal remains asserted for the duration of the two transfers. The delay between transfers (tDT) is notinserted between the transfers.Figure 11-19 shows the timing diagram for two 4-bit transfers with CPHA = 1 and CONT = 1.Figure 11-19. Example of continuous transfer (CPHA = 1, CONT = 1)In Figure 11-19, the period length at the start of the next transfer is the sum of tASC and tCSC. It does notinclude a half-clock period. The default settings for these provide a total of four system clocks. In manysituations, tASC and tCSC must be increased if a full half-clock period is required.When the CONT bit = 1 and the CS signals for the next transfer are different from the present transfer, theCS signals behave as if the CONT bit was not set.Switching CTAR registers or changing which PCS signals are asserted between frames while usingContinuous Selection can cause errors in the transfer. The PCS signal should be negated before CTAR isswitched or different PCS signals are selected.11.8.5.6 Clock polarity switching between DSPI transfersIf you want to switch polarity between non-continuous DSPI frames, it is important to remember that theedge generated by the change in the idle state of the clock occurs one system clock before the assertion ofthe chip select for the next frame.NOTEIt is mandatory to fill the TX FIFO with the number of entries that will beconcatenated together under one PCS assertion for both master and slavebefore the TX FIFO becomes empty. For example, while transmitting inMaster mode, it should be ensured that the last entry in the TX FIFO, afterwhich TX FIFO becomes empty, must have the CONT bit in commandframe as deasserted (CONT bit = 0). While operating in Slave mode, itshould be ensured that when the last entry in the TX FIFO is completelytransmitted (that is, the corresponding TCF flag is asserted and TX FIFO isempty), the slave should be de-selected for any further serialcommunication. Otherwise, an underflow error occurs.SCK(CPOL = 0)CStASCSCK(CPOL = 1)Master SOUTt CSCtCSCt CSC = CS to SCK delay.t ASC = After SCK delay.Master SIN
