Deserial Serial Peripheral Interface (DSPI)MPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 32711.8.7.4 Transmit FIFO underflow interrupt request (TFUF)The transmit FIFO underflow request indicates that an underflow condition in the TX FIFO has occurred.The transmit underflow condition is detected only for DSPI modules operating in Slave mode and SPIconfiguration. The TFUF bit is set when the TX FIFO of a DSPI operating in Slave mode and SPIconfiguration is empty, and a transfer is initiated from an external SPI master. If the TFUF bit is set whilethe TFUF_RE bit in the DSPIx_RSER is set, an interrupt request is generated.11.8.7.5 Receive FIFO drain interrupt or DMA request (RFDF)The receive FIFO drain request indicates that the RX FIFO is not empty. The receive FIFO drain requestis generated when the number of entries in the RX FIFO is not zero, and the RFDF_RE bit in theDSPIx_RSER is set. The RFDF_DIRS bit in the DSPIx_RSER selects whether a DMA request or aninterrupt request is generated.11.8.7.6 Receive FIFO overflow interrupt request (RFOF)The receive FIFO overflow request indicates that an overflow condition in the RX FIFO has occurred. Areceive FIFO overflow request is generated when RX FIFO and shift register are full and a transfer isinitiated. The RFOF_RE bit in the DSPIx_RSER must be set for the interrupt request to be generated.Depending on the state of the ROOE bit in the DSPIx_MCR, the data from the transfer that generated theoverflow is either ignored or shifted into the shift register. If the ROOE bit is set, the incoming data isshifted into the shift register. If the ROOE bit is negated, the incoming data is ignored.11.8.7.7 FIFO overrun request (TFUF) or (RFOF)The FIFO overrun request indicates that at least one of the FIFOs in the DSPI has exceeded its capacity.The FIFO overrun request is generated by logically ORing together the RX FIFO overflow and TX FIFOunderflow signals.11.8.8 Power-saving featuresThe DSPI supports three power-saving strategies:• External stop mode• Module Disable mode—clock gating of non-memory mapped logic• Clock gating of slave interface signals and clock to memory-mapped logic11.8.8.1 External Stop modeThe DSPI supports the Stop mode protocol. When a request is made to enter External Stop mode, the DSPIblock acknowledges the request by negating ipg_stop_ack. When the DSPI is ready to have its clocks shutoff, the ipg_stop_ack signal is asserted. If a serial transfer is in progress, the DSPI waits until it reaches theframe boundary before it asserts ipg_stop_ack. While the clocks are shut off, the DSPI memory-mappedlogic is not accessible. The states of the interrupt and DMA request signals cannot be changed while inExternal Stop mode. Implementation of IPI Green Line Stop mode in an SoC is optional.
