IEEE 1149.1 Test Access Port Controller (JTAGC)MPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 71919.7.1 Instruction registerThe JTAGC uses a 5-bit instruction register as shown in Figure 19-2. The instruction register allowsinstructions to be loaded into the module to select the test to be performed or the test data register to beaccessed or both. Instructions are shifted in through TDI while the TAP controller is in the Shift-IR state,and latched on the falling edge of TCK in the Update-IR state. The latched instruction value can only bechanged in the Update-IR and Test-Logic-Reset TAP controller states. Synchronous entry into theTest-Logic-Reset state results in the IDCODE instruction being loaded on the falling edge of TCK.Asynchronous entry into the Test-Logic-Reset state results in asynchronous loading of the IDCODEinstruction. During the Capture-IR TAP controller state, the instruction shift register is loaded with thevalue 0b10101, making this value the register’s read value when the TAP controller is sequenced into theShift-IR state.19.7.2 Bypass registerThe bypass register is a single-bit shift register path selected for serial data transfer between TDI and TDOwhen the BYPASS or the reserve instructions are active. After entry into the capture-DR state, thesingle-bit shift register is set to a logic 0. Therefore, the first bit shifted out after selecting the bypassregister is always a logic 0.19.7.3 Device Identification registerThe device identification register, shown in Figure 19-3, allows the part revision number, design center,part identification number, and manufacturer identity code to be determined through the TAP. The deviceidentification register is selected for serial data transfer between TDI and TDO when the IDCODEinstruction is active. Entry into the capture-DR state while the device identification register is selectedloads the IDCODE into the shift register to be shifted out on TDO in the Shift-DR state. No action occursin the Update-DR state.4 3 2 1 0R 1 0 1 0 1W Instruction CodeReset 0 0 0 0 1Figure 19-2. 5-Bit Instruction RegisterIR[4:0]: 0_0001 (IDCODE) Access: R/O0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R PRN DC PIN MIC IDWReset 0 0 0 0 1 0 1 0 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1Figure 19-3. Device Identification Register
