Error Correction Status Module (ECSM)MPC5606S Microcontroller Reference Manual, Rev. 7526 Freescale Semiconductorreset as signaled by device reset input signals. The MRSR can only be read from the IPS programmingmodel. Any attempted write is ignored.See Figure 16-3 and Table 16-4 for the Miscellaneous Reset Status Register definition.16.4.2.4 Miscellaneous Wakeup Control Register (MWCR)Implementation of low-power modes and exit from these modes via an interrupt requires communicationbetween the ECSM, the interrupt controller, and external logic typically associated with phase-locked loopclock generation circuitry. The Miscellaneous Wakeup Control Register (MWCR) provides an 8-bitregister controlling entry into these types of low-power modes as well as definition of the interrupt levelneeded to exit the mode.The following sequence of operations is generally needed to enable this functionality. Note that the exactdetails are likely to be system-specific.1. The processor core loads the appropriate data value into the MWCR, setting the ENBWCR bit andthe desired interrupt priority level.2. At the appropriate time, the processor ceases execution. The exact mechanism varies by processorcore. In some cases, a processor-is-stopped status is signaled to the ECSM and external logic. Thisassertion, if properly enabled by MWCR[ENBWCR], causes the ECSM output signalenter_low_power_mode to be set. This, in turn, causes the selected external, low-power mode, tobe entered, and the appropriate clock signals disabled. In most implementations, there are multiplelow-power modes, where the exact clocks to be disabled vary across the different modes.3. After entering the low-power mode, the interrupt controller enables a special combinational logicpath which evaluates all unmasked interrupt requests. The device remains in this mode until anevent which generates an unmasked interrupt request with a priority level greater than the valueprogrammed in the MWCR[PRILVL] occurs.4. Once the appropriately high interrupt request level arrives, the interrupt controller signals itspresence, and the ECSM responds by asserting an exit_low_power_mode signal.5. The external logic senses the assertion of the exit signal, and re-enables the appropriate clocksignals.Address: Base + 0x000F Access: User read-only0 1 2 3 4 5 6 7R POR OFPLR 0 0 0 0 0 0WReset 0 1 0 0 0 0 0 0Figure 16-3. Miscellaneous Reset Status Register (MRSR)Table 16-4. Miscellaneous Reset Status (MRSR) field descriptionsName Description0PORPower-On Reset1 Last recorded event was caused by a power-on reset (based on a device input signal)1DIRDevice Input Reset1 Last recorded event was a reset caused by a device input reset
