Interrupt Controller (INTC)MPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 759The interrupt acknowledge register provides a value that can be used to load the address of an ISR from avector table. The vector table can be composed of addresses of the ISRs specific to their respectiveinterrupt vectors.In software vector mode, the INTC_IACKR has side effects from reads. Therefore, it must not bespeculatively read while in this mode. The side effects are the same regardless of the size of the read.Reading the INTC_IACKR does not have side effects in hardware vector mode.21.5.2.4 INTC End-of-Interrupt Register (INTC_EOIR)Writing to the end-of-interrupt register signals the end of the servicing of the interrupt request. When theINTC_EOIR is written, the priority last pushed on the LIFO is popped into INTC_CPR. An exception tothis behavior is described in Section 21.4.1.2, Hardware vector mode. The values and size of data writtento the INTC_EOIR are ignored. The values and sizes written to this register neither update theINTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytesof all 0s to the INTC_EOIR.Reading the INTC_EOIR has no effect on the LIFO.21.5.2.5 INTC Software Set/Clear Interrupt Registers(INTC_SSCIR0_3–INTC_SSCIR4_7)Offset 0x0018 Access: write only0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 21-5. INTC End-of-Interrupt Register (INTC_EOIR)Offset: 0x0020 Access: User read/write0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R 0 0 0 0 0 0 0 CLR0 0 0 0 0 0 0 0 CLR1W SET0 SET1Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R 0 0 0 0 0 0 0 CLR2 0 0 0 0 0 0 0 CLR3W SET2 SET3Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 21-6. INTC Software Set/Clear Interrupt Register 0–3 (INTC_SSCIR[0:3])
