Flash MemoryMPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 63917.4.1.3 Modes of operationThe PFLASH2P_LCA module does not support any special modes of operation. Its operation is drivenfrom the AMBA-AHB memory references it receives from the platform’s bus masters. Its configuration isdefined by the setting of its programming model registers, physically located as part of the flash arraymodules.17.4.2 External signal descriptionsThe PFLASH2P_LCA does not directly interface with any external signals. As shown in Figure 17-42 andFigure 17-43, its primary internal interfaces include two input connections from AMBA-AHB crossbar (ormemory protection unit) slave ports and output connections with up to three banks (2 code and 1 data) offlash memory, each containing one or more instantiations of the low-cost flash array. Additionally, theoperating configuration for the PFLASH2P_LCA is defined by the contents of certain bank0 array0registers which are inputs to the module.A summary of the major PFLASH2p_LCA internal connections is shown in Table 17-61.17.4.3 Memory map and register definitionThere are two memory maps associated with the PFLASH2P_LCA: one for the flash memory space andanother for the program-visible control and configuration registers. The flash memory space is accessedvia the AMBA-AHB ports while the program-visible registers are accessed via the slave peripheral bus.Details on both memory spaces are provided in Section 17.4.3.1, Memory map.There are no program-visible registers that physically reside inside the PFLASH2P_LCA. Rather, thePFLASH2P_LCA receives control and configuration information from the flash array controller(s) todetermine the operating configuration. These are part of the flash array’s configuration registers mappedinto its slave peripheral (IPS) address space but are described here.17.4.3.1 Memory mapFirst, consider the flash memory space accessed via transactions from the PFLASH2P_LCA’s AHB ports.To support the three separate flash memory banks, the PFLASH2P_LCA controller uses address bits 23and 19 (haddr[23, 19]) to steer the access to the appropriate memory bank. The address decode allocatestwo 4 Mbyte spaces for bank0 and bank2 and an 8 Mbyte space for bank1. In addition to the actual flashmemory regions, there are shadow and test sectors included in the system memory map. TheTable 17-61. PFLASH2P_LCA Module ConnectionsPFLASH2P_LCA Connection DescriptionInput p0 Processor CoreInput p1 Non-core MastersOutput b0 Bank0, Code FlashOutput b1 Bank1, Data FlashOutput b2 Bank2, Code Flash
