Quad Serial Peripheral Interface (QuadSPI)MPC5606S Microcontroller Reference Manual, Rev. 71002 Freescale Semiconductor30.4.2 AMBA bus register memory mapQSPI_AMBA_BASE defines the address to be used as start address of the serial flash device.FIFO RegistersQSPI_BASE+0x034 PUSH TX FIFO Register (QSPI_PUSHR)QSPI_BASE+0x038 POP RX FIFO Register (QSPI_POPR)QSPI_BASE+0x03C–QSPI_BASE+0x074Transmit FIFO Registers 0 – 14 (QSPI_TXFR0 – QSPI_TXFR14)QSPI_BASE+0x078 ReservedQSPI_BASE+0x07C–QSPI_BASE+0x0B4RX FIFO Registers 0 – 14 (QSPI_RXFR0 – QSPI_RXFR14)QSPI_BASE+0x0B8–QSPI_BASE+0x0FCReservedRegisters valid in SFM mode only2QSPI_BASE+0x100 Serial Flash Address Register (QSPI_SFAR)QSPI_BASE+0x104 Instruction Code Register (QSPI_ICR)QSPI_BASE+0x108 Sampling Register (QSPI_SMPR)QSPI_BASE+0x10C RX Buffer Status Register (QSPI_RBSR)QSPI_BASE+0x110–QSPI_BASE+0x148RX Buffer Data Registers 0–14 (QSPI_RBDR0–QSPI_RBDR14)QSPI_BASE+0x14C ReservedQSPI_BASE+0x150 TX Buffer Status Register (QSPI_TBSR)QSPI_BASE+0x154 TX Buffer Data Register (QSPI_TBDR)QSPI_BASE+0x158 AMBA Control Register (QSPI_ACR)QSPI_BASE+0x15C Serial Flash Mode Status Register (QSPI_SFMSR)QSPI_BASE+0x160 Serial Flash Mode Flag Register (QSPI_SFMFR)QSPI_BASE+0x164 SFM Interrupt and DMA Request Select and Enable Register (QSPI_SFMRSER)QSPI_BASE+0x168–QSPI_BASE+0x1FCReserved1 These registers must not be written if the QuadSPI module is in SFM mode.2 These registers must not be written if the QuadSPI module is in SPI Master or SPI Slave modeTable 30-6. QuadSPI IP bus memory map (continued)Address Register name
