Mode Entry Module (MC_ME)MPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 945The current system clock configuration can be observed by reading the S_SYSCLK bit field of the ME_GSregister, which is updated after every system clock switching. Until the target clock is available, the systemuses the previous clock configuration.System clock switching starts only after• The Clock sources switch-on process has completed if the target system clock source needs to beswitched on• The FMPLL0 Switch-On process has completed if the target system clock is the primary freq. mod.PLL• The Peripheral Clocks Disable process is completed in order not to change the system clockfrequency before peripherals close their internal activitiesAn overview of system clock source selection possibilities for each mode is shown in Table 25-17. A ‘’indicates that a given clock source is selectable for a given mode.25.4.3.16 Power Domain #2 Switch-OffBased on the device mode and the MC_PCU’s power configuration register PCU_PCONF2, the powerdomain #2 is controlled by the MC_PCU.If a mode change translates to a power-down of the power domain, then the MC_PCU starts thepower-down sequence. The MC_PCU acknowledges the completion of the power-down sequence withrespect to the new mode, and the MC_ME uses this information to update the mode transition status. Thisstep is executed only after the Peripheral Clocks Disable process has completed.25.4.3.17 Pad Switch-OffIf the PDO bit of the ME_ mode>_MC register is 1 then• The outputs of the pads are forced to the high impedance state if the target mode is Safe or TestTable 25-17. MC_ME system clock selection overviewSystem ClockSourceModeReset Test Safe DRUN Run0…3 Halt Stop Standby16MHz int. RCosc.(default)(default)(default)(default)(default)(default)(default)div. 16MHz int.RC osc. div. 4-16MHzext. osc. primary freq.mod. PLL system clock isdisabled1 Disabling the system clock during Test mode will require a reset in order to exit Test mode (default)
