Inter-Integrated Circuit Bus Controller Module (I2 C)MPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 74320.5.2.2 Slave Address TransmissionThe first byte of data transfer immediately after the START signal is the slave address transmitted by themaster. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desireddirection of data transfer.1 = Read transfer—the slave transmits data to the master0 = Write transfer—the master transmits data to the slaveOnly the slave with a calling address that matches the one transmitted by the master will respond bysending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 20-10).No two slaves in the system may have the same address. If the I2C Bus is master, it must not transmit anaddress that is equal to its own slave address. The I2C Bus cannot be master and slave at the same time.However, if arbitration is lost during an address cycle the I2C Bus will revert to Slave mode and operatecorrectly, even if it is being addressed by another master.20.5.2.3 Data TransferOnce successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a directionspecified by the R/W bit sent by the calling master.All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-addressinformation for the slave device.Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable whileSCL is high as shown in Figure 20-10. There is one clock pulse on SCL for each data bit, the MSB beingtransferred first. Each data byte must be followed by an acknowledge bit, which is signaled from thereceiving device by pulling the SDA low at the ninth clock. Therefore, one complete data byte transferneeds nine clock pulses.If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. Themaster can then generate a stop signal to abort the data transfer or a start signal (repeated start) tocommence a new calling.If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'endof data' to the slave, so the slave releases the SDA line for the master to generate a stop or START signal.20.5.2.4 Stop SignalThe master can terminate the communication by generating a stop signal to free the bus. However, themaster may generate a START signal followed by a calling command without generating a stop signal first.This is called repeated START. A stop signal is defined as a low-to-high transition of SDA while SCL isat logical “1” (see Figure 20-10).The master can generate a stop even if the slave has generated an acknowledge, at which point the slavemust release the bus.
