Wakeup Unit (WKPU)MPC5606S Microcontroller Reference Manual, Rev. 71240 Freescale SemiconductorNOTEReserved registers will read as 0, writes will have no effect. If supported andenabled by the SoC, a transfer error will be issued when trying to accesscompletely reserved register space.41.4.2 Register descriptionThis section describes in address order all the Wakeup Unit registers. Each description includes a standardregister diagram with an associated figure number. Details of register bit and field function follow theregister diagrams, in bit order. The numbering convention of register is MSB = 0, however the numberingof internal field is LSB = 0. For example, EIF[5] = WISR[26].41.4.2.1 NMI Status Flag Register (NSR)This register holds the non-maskable interrupt status flags.0x0020–0x0027 Reserved0x0028 Wakeup/Interrupt Rising-Edge Event EnableRegisterWIREER 32 320x002C Wakeup/Interrupt Falling-Edge Event EnableRegisterWIFEER 32 320x0030 Wakeup/Interrupt Filter Enable Register WIFER 32 320x0034 Wakeup/Interrupt Pullup Enable Register WIPUER 32 320x0038–0x03FFF ReservedAddress: Base + 0x0000 Access: User read/write (write 1 to clear)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R NIF NOVF 0 0 0 0 0 0 0 0 0 0 0 0 0 0W w1c w1cReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 41-2. NMI Status Flag Register (NSR)Table 41-2. WKPU memory map (continued)Address offset Use Abbreviation Size Supportedaccess sizes
