Interrupt Controller (INTC)MPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 779interrupt_exception_handler_continuedx:code to create stack frame, save working register, and save SRR0 and SRR1wrteei 1 # enable processor recognition of interruptscode to save rest of context required by e500 EABIbl ISRx # branch to ISR for interrupt with vector xepilog:code to restore most of context required by e500 EABI# Popping the LIFO after the restoration of most of the context and the disabling of processor# recognition of interrupts eases the calculation of the maximum stack depth at the cost of# postponing the servicing of the next interrupt request.mbar # ensure store to clear flag bit has completedlis r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR addressli r4,0x0 # form 0 to write to INTC_EOIRwrteei 0 # disable processor recognition of interruptsstw r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower prioritycode to restore SRR0 and SRR1, restore working registers, and delete stack framerfiISRx:code to service the interrupt eventcode to clear flag bit which drives interrupt request to INTCblr # branch to epilog21.7.3 ISR, RTOS, and task hierarchyThe RTOS and all of the tasks under its control typically execute with PRI in INTC current priority register(INTC_CPR) having a value of 0. The RTOS will execute the tasks according to whatever priority schemethat it may have, but that priority scheme is independent and has a lower priority of execution than thepriority scheme of the INTC. In other words, the ISRs execute above INTC_CPR priority 0 and outsidethe control of the RTOS, the RTOS executes at INTC_CPR priority 0, and while the tasks execute atdifferent priorities under the control of the RTOS, they also execute at INTC_CPR priority 0.If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then thetask’s priority can be elevated in the INTC_CPR while the shared resource is being accessed.An ISR whose PRIn in INTC priority select registers (INTC_PSR0_3–INTC_PSR204_206) has a valueof 0 will not cause an interrupt request to the processor, even if its peripheral or software settable interruptrequest is asserted. For a peripheral interrupt request, not setting its enable bit or disabling the mask bitwill cause it to remain negated, which consequently also will not cause an interrupt request to theprocessor. Since the ISRs are outside the control of the RTOS, this ISR will not run unless called by anotherISR or the interrupt exception handler, perhaps after executing another ISR.
