DMA Channel Mux (DMACHMUX)MPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 451All registers are accessible via 8-bit, 16-bit, or 32-bit accesses. However, 16-bit accesses must be alignedto 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example,CHCONFIG0 through CHCONFIG3 are accessible by a 32-bit read/write to address Base + 0x00, butperforming a 32-bit access to address Base + 0x01 is illegal.13.3.1 Register descriptionsThe following memory-mapped registers are available in the DMA channel mux.13.3.1.1 Channel configuration registersEach of the DMA channels can be independently enabled/disabled and associated with one of the DMAslots (peripheral slots or always-on slots) in the system.Address: Base + #n Access: User read/write0 1 2 3 4 5 6 7R ENBL TRIG SOURCEWReset 0 0 0 0 0 0 0 0Figure 13-2. Channel Configuration Registers (CHCONFIG#n)Table 13-2. CHCONFIGxx field descriptionsField DescriptionENBL DMA Channel Enable. ENBL enables the DMA Channel0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channelenables/disables, which should be used to disable or re-configure a DMA channel.1 DMA channel is enabled.TRIG DMA Channel Trigger Enable (for triggered channels only). TRIG enables the periodic triggercapability for the DMA Channel.0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specifiedsource to the DMA channel.1 Triggering is enabled.SOURCE DMA Channel Source (slot). SOURCE specifies which DMA source, if any, is routed to a particularDMA channel. Please check your SoC guide for further details about the peripherals and their slotnumbers.Table 13-3. Channel and trigger enablingENBL TRIG Function Mode0 X DMA channel is disabled Disabled mode1 0 DMA channel is enabled with no triggering (transparent) Normal mode1 1 DMA channel is enabled with triggering Periodic Trigger mode
