Display Control Unit (DCU)MPC5606S Microcontroller Reference Manual, Rev. 7384 Freescale Semiconductor12.3.4.28 Parameter Error Status (PARR_ERR) registerFigure 12-37 shows the parameter error status register.An error in a layer can occur under the following conditions:a) Number of pixels in a tile > maximum tile memory size in case of Tile bandwidth optimizedmode (when in internal memory mode)b) There is an automatic error checking mechanism when a layer is enabled that detects anon-valid horizontal size and color format combination. See Section 12.4.5.3, Layer size andpositioning, for details.These errors are grouped into a single bit error for each layer. The parameter error specific to each layer issignaled only when the layer is enabled.Table 12-31. PDI Status Mask Register field descriptionsField Description22m_pdi_blanking_errpdi_blanking_err interrupt mask0 Interrupt is not masked1 Interrupt is masked23m_pdi_ecc_err2pdi_ecc_err2 interrupt mask0 Interrupt is not masked1 Interrupt is masked24m_pdi_ecc_err1pdi_ecc_err1 interrupt mask0 Interrupt is not masked1 Interrupt is masked25m_pdi_lock_lostpdi_lock_lost interrupt mask0 Interrupt is not masked1 Interrupt is masked26m_pdi_lock_detpdi_lock_det interrupt mask0 Interrupt is not masked1 Interrupt is masked27m_pdi_vsync_detpdi_vsync_det interrupt mask0 Interrupt is not masked1 Interrupt is masked28m_pdi_hsync_detpdi_hsync_det interrupt mask0 Interrupt is not masked1 Interrupt is masked29m_pdi_de_detpdi_de_det interrupt mask0 Interrupt is not masked1 Interrupt is masked30m_pdi_clk_lostpdi_clk_lost interrupt mask0 Interrupt is not masked1 Interrupt is masked31m_pdi_clk_detpdi_clk_det interrupt mask0 Interrupt is not masked1 Interrupt is masked
