Mode Entry Module (MC_ME)MPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 91725.3.2.4 Interrupt Status Register (ME_IS)This register provides the current interrupt status.Address 0xC3FD_C00C Access: Supervisor read/write0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R0 0 0 0 0 0 0 0 0 0 0 0I_ICONFI_IMODEI_SAFEI_MTCW w1c w1c w1c w1cReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 25-5. Interrupt Status Register (ME_IS)Table 25-7. Interrupt Status Register (ME_IS) field descriptionsField DescriptionI_ICONF Invalid mode configuration interrupt — This bit is set whenever a write operation to ME_<mode>_MC registerswith invalid mode configuration is attempted. It is cleared by writing a 1 to this bit.0 No invalid mode configuration interrupt occurred1 Invalid mode configuration interrupt is pendingNote: The I_ICONF bit will not detect that modes that select a PLL to be active also have the FXOSC enabled.Therefore, always ensure that any mode that selects PLL as the system clock also has the associatedFXOSC bit set.I_IMODE Invalid mode interrupt — This bit is set whenever an invalid mode transition is requested. It is cleared by writinga 1 to this bit.0 No invalid mode interrupt occurred1 Invalid mode interrupt is pendingI_SAFE Safe mode interrupt — This bit is set whenever the device enters Safe mode on hardware requests generatedin the system. It is cleared by writing a 1 to this bit.0 No Safe mode interrupt occurred1 Safe mode interrupt is pendingI_MTC Mode transition complete interrupt — This bit is set whenever the mode transition process completes(S_MTRANS transits from 1 to 0). It is cleared by writing a 1 to this bit. This mode transition interrupt bit will notbe set while entering low-power modes Halt, Stop, or Standby.0 No mode transition complete interrupt occurred1 Mode transition complete interrupt is pending
