Analog-to-Digital Converter (ADC)MPC5606S Microcontroller Reference Manual, Rev. 7160 Freescale Semiconductor5.4.8 Delay registers5.4.8.1 Decode Signals Delay Register (DSDR)Reset value: 0x0000_00005.4.8.2 Power-down Exit Delay Register (PDEDR)Reset value: 0x0000_0000Address: Base + 0x00C4 Access: User read/write0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R 0 0 0 0 0 0 0 0 DSD[0:7]WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 5-24. Decode Signals Delay Register (DSDR)Table 5-22. Decode Signals Delay Register (DSDR) field descriptionsField Description0–23 ReservedA write of any value has no effect. The read value is always 0.24–31DSD[0:7]Delay between the external decode signals and the start of the sampling phaseIt is used to take into account the settling time of the external multiplexer.The decode signal delay is calculated as: DSD × 1/frequency of system clock. For the case when ADCclock = Peripheral Clock/2, the DSD bit field has to be incremented by 2 to see an additional ADC clockcycle delay on the decode signal. For example:0000 0 ADC clock cycle delay.0010 1 ADC clock cycle delay.0100 2 ADC clock cycle delay.0110 3 ADC clock cycle delay.